Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic
Description
18
19
20
P4.6/AD14/PLAO[14]
General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic
Array Output Element 14.
General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic
Array Output Element 15.
Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM
is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7/External Memory Select 0.
P4.7/AD15/PLAO[15]
BM/P0.0/CMPOUT/PLAI[7]/MS0
21
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
22
23
24
TCK
TDO
P0.2/PWM2L/BHE
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory
Byte High Enable.
25
26
27
IOGND
IOVDD
LVDD
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
28
29
DGND
Ground for Core Logic.
P3.0/AD0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-Side
Output/Programmable Logic Array Input Element 8.
30
31
32
33
P3.1/AD1/PWM0L/PLAI[9]
P3.2/AD2/PWM1H/PLAI[10]
P3.3/AD3/PWM1L/PLAI[11]
P2.4/PWM0H/MS0
General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-Side
Output/Programmable Logic Array Input Element 9.
General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-Side
Output/Programmable Logic Array Input Element 10.
General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-Side
Output/Programmable Logic Array Input Element 11.
General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory
Select 0.
34
35
P0.3/TRST/A16/ADCBUSY
P2.5/PWM0L/MS1
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output.
General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory
Select 1.
36
P2.6/PWM1H/MS2
General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory
Select 2.
37
38
RST
Reset Input, Active Low.
P3.4/AD4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-Side
Output/Programmable Logic Array Input 12.
39
40
P3.5/AD5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-Side
Output/Programmable Logic Array Input Element 13.
IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/
External Memory Select 1.
41
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2 Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External
Memory Select 2.
42
43
CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
P2.0/SPM9/PLAO[5]/
44
45
XCLKO
XCLKI
Output from the Crystal Oscillator Inverter.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
Rev. F | Page 29 of 104
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