Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Pin No. Mnemonic
Description
37
38
39
40
P3.6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input
Element 14.
General-Purpose Input and Output Port 3.7/PWM Synchronization Input and Output/
Programmable Logic Array Input Element 15.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable
Logic Array Output Element 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
P3.7/PWMSYNC/PLAI[15]
P1.7/SPM7/PLAO[0]
P1.6/SPM6/PLAI[6]
41
42
43
44
45
IOGND
IOVDD
P4.0/PLAO[8]
P4.1/PLAO[9]
P1.5/SPM5/PLAI[5]/IRQ3
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.
General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
46
47
48
49
50
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable
Logic Array Input Element 4/External Interrupt Request 2, Active High.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic
Array Input Element 1.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
51
52
53
54
55
P4.2/PLAO[10]
P4.3/PLAO[11]
P4.4/PLAO[12]
P4.5/PLAO[13]
VREF
General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.
General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.
General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.
General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the
internal reference.
56
57
58
59
60
61
62
63
64
0
DACREF
DACGND
AGND
AVDD
DACVDD
ADC0
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
Ground for the DAC. Typically connected to AGND.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
3.3 V Power Supply for the DACs. Must be connected to AVDD.
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
ADC1
ADC2/CMP0
ADC3/CMP1
EP
Exposed Pad. The pin configuration for the ADuC7024/ADuC7025 LFCSP_VQ has an exposed pad
that must be soldered for mechanical purposes and left unconnected.
Rev. F | Page 27 of 104
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