ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Ball No.
Mnemonic
Description
D7
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable
Logic Array Input Element 6.
D8
E1
E2
E3
E4
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
DAC3 Voltage Output/ADC Input 15.
DAC3/ADC15
DAC2/ADC14
DAC1/ADC13
P3.0/PWM0H/PLAI[8]
DAC2 Voltage Output/ADC Input 14.
DAC1 Voltage Output/ADC Input 13.
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
E5
E6
E7
P3.2/PWM1H/PLAI[10]
P1.5/SPM5/PLAI[5]/IRQ3
P3.7/PWMSYNC/PLAI[15]
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable
Logic Array Input Element 5/External Interrupt Request 3, Active High.
General-Purpose Input and Output Port 3.7/PWM Synchronization/Programmable Logic
Array Input Element 15.
E8
F1
F2
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
JTAG Test Port Input, Test Data In. Debug and download access.
P4.6/PLAO[14]
TDI
F3
F4
DAC0/ADC12
DAC0 Voltage Output/ADC Input 12.
P3.1/PWM0L/PLAI[9]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
F5
P3.3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
F6
F7
RST
Reset Input, Active Low.
P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External
Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array
Output Element 4.
F8
XCLKO
Output from the Crystal Oscillator Inverter.
G1
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot mode. The ADuC7028 enters UART download mode if BM is low
at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
G2
G3
G4
G5
P4.7/PLAO[15]
TMS
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
JTAG Test Port Input, Test Mode Select. Debug and download access.
TDO
JTAG Test Port Output, Test Data Out. Debug and download access.
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal
Output.
G6
G7
G8
H1
P3.4/PWM2H/PLAI[12]
P3.5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable
Logic Array Output Element 5/Start Conversion Input Signal for ADC.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
P2.0/SPM9/PLAO[5]/CONVSTART
P0.6/T1/MRST/PLAO[3]
H2
H3
H4
H5
TCK
JTAG Test Port Input, Test Clock. Debug and download access.
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
IOGND
IOVDD
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
H6
H7
DGND
Ground for Core Logic.
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
H8
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2.
Rev. F | Page 32 of 104
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