ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ADuC7026/ADuC7027
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
1
2
3
4
5
6
7
8
9
60 P1.2/SPM2/PLAI[2]
59 P1.3/SPM3/PLAI[3]
58 P1.4/SPM4/PLAI[4]/IRQ2
57 P1.5/SPM5/PLAI[5]/IRQ3
56 P4.1/AD9/PLAO[9]
55 P4.0/AD8/PLAO[8]
PIN 1
INDICATOR
54 IOV
53 IOGND
DD
GND
REF
ADuC7026/
ADuC7027
ADCNEG
52 P1.6/SPM6/PLAI[6]
51 P1.7/SPM7/PLAO[0]
DAC0/ADC12 10
DAC1/ADC13 11
DAC2/ADC14 12
DAC3/ADC15 13
TMS 14
50 P2.2/RS/PWM0 /PLAO[7]
L
TOP VIEW
49 P2.1/WS/PWM0 /PLAO[6]
(Not to Scale)
H
48 P2.7/PWM1 /MS3
L
47 P3.7/AD7/PWM
46 P3.6/AD6/PWM
45 XCLKI
/PLAI[15]
SYNC
/PLAI[14]
TDI 15
TRIP
P0.1/PWM2 /BLE 16
H
P2.3/AE 17
P4.6/AD14/PLAO[14] 18
P4.7/AD15/PLAO[15] 19
44 XCLKO
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
42 P2.0/SPM9/PLAO[5]/CONV
START
/PLAO[2]/MS2
BM/P0.0/CMP
/PLAI[7]/MS0 20
41 IRQ1/P0.5/ADC
OUT
BUSY
Figure 25. 80-Lead LQFP Pin Configuration (ADuC7026/ADuC7027)
Table 13. Pin Function Descriptions (ADuC7026/ADuC7027)
Pin No. Mnemonic
Description
1
2
3
4
5
6
7
8
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
GNDREF
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
Single-Ended or Differential Analog Input 10.
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
9
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
10
11
12
13
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7027.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7027.
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not
present on the ADuC7027.
DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not
present on the ADuC7027.
14
15
16
TMS
TDI
P0.1/PWM2H/BLE
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access.
General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
Byte Low Enable.
17
P2.3/AE
General-Purpose Input and Output Port 2.3/External Memory Access Enable.
Rev. F | Page 28 of 104
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