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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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Data Sheet  
ADuC7019/20/21/22/24/25/26/27/28/29  
ADUC7028  
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
BOTTOM VIEW  
(Not to Scale)  
Figure 26. 64-Ball CSP_BGA Pin Configuration (ADuC7028)  
Table 14. Pin Function Descriptions (ADuC7028)  
Ball No.  
Mnemonic  
ADC3/CMP1  
DACVDD  
Description  
A1  
A2  
Single-Ended or Differential Analog Input 3/Comparator Negative Input.  
3.3 V Power Supply for the DACs. Must be connected to AVDD.  
3.3 V Analog Power.  
A3  
AVDD  
A4  
AGND  
Analog Ground. Ground reference point for the analog circuitry.  
Ground for the DAC. Typically connected to AGND.  
General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10.  
A5  
DACGND  
A6  
P4.2/PLAO[10]  
P1.1/SPM1/PLAI[1]  
A7  
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable  
Logic Array Input Element 1.  
A8  
P1.2/SPM2/PLAI[2]  
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable  
Logic Array Input Element 2.  
B1  
B2  
B3  
B4  
B5  
ADC4  
Single-Ended or Differential Analog Input 4.  
ADC2/CMP0  
ADC1  
Single-Ended or Differential Analog Input 2/Comparator Positive Input.  
Single-Ended or Differential Analog Input 1.  
DACREF  
VREF  
External Voltage Reference for the DACs. Range: DACGND to DACVDD.  
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor when using the  
internal reference.  
B6  
B7  
B8  
P1.0/T1/SPM0/PLAI[0]  
P1.4/SPM4/PLAI[4]/IRQ2  
P1.3/SPM3/PLAI[3]  
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/  
Programmable Logic Array Input Element 0.  
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable  
Logic Array Input Element 4/External Interrupt Request 2, Active High.  
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable  
Logic Array Input Element 3.  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
D1  
ADC6  
Single-Ended or Differential Analog Input 6.  
ADC5  
Single-Ended or Differential Analog Input 5.  
ADC0  
Single-Ended or Differential Analog Input 0.  
P4.5/PLAO[13]  
P4.3/PLAO[11]  
P4.0/PLAO[8]  
P4.1/PLAO[9]  
IOGND  
General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13.  
General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11.  
General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8.  
General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9.  
Ground for GPIO (see Table 78). Typically connected to DGND.  
ADCNEG  
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be  
connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V.  
D2  
GNDREF  
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply  
should be separated from IOGND and DGND.  
D3  
D4  
D5  
ADC7  
Single-Ended or Differential Analog Input 7.  
P4.4/PLAO[12]  
P3.6/PWMTRIP/PLAI[14]  
General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12.  
General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array  
Input Element 14.  
D6  
P1.7/SPM7/PLAO[0]  
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable  
Logic Array Output Element 0.  
Rev. F | Page 31 of 104