Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020 7021 7022 Mnemonic
Description
38
39
40
1
37
38
39
40
36
37
38
39
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/
Comparator Negative Input.
2
‒
‒
‒
‒
‒
3
1
2
40
1
ADC4
ADC5
Single-Ended or Differential Analog Input 4.
Single-Ended or Differential Analog Input 5.
3
4
2
3
4
5
6
ADC6
ADC7
ADC8
ADC9
GNDREF
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
‒
‒
5
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4
5
6
7
6
7
‒
‒
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
‒
‒
‒
‒
DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
must be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15 (see Figure 53).
8
8
7
TMS
Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOVDD. In some cases, an external
pull-up resistor (~100K) is also required to ensure that the part does not
enter an erroneous state.
9
10
9
10
8
9
TDI
Test Data In, JTAG Test Port Input. Debug and download access.
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter
serial download mode if BM is low at reset and execute code if BM is
pulled high at reset through a 1 kΩ resistor/General-Purpose Input and
Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
11
12
11
12
10
11
P0.6/T1/MRST/PLAO[3]
TCK
Multifunction Pin. Driven low after reset. General-Purpose Output Port 0.6/
Timer1 Input/Power-On Reset Output/Programmable Logic Array Output
Element 3.
Test Clock, JTAG Test Port Input. Debug and download access. This pin has
an internal pull-up resistor to IOVDD. In some cases an external pull-up
resistor (~100K) is also required to ensure that the part does not enter an
erroneous state.
13
14
15
13
14
15
12
13
14
TDO
IOGND
IOVDD
Test Data Out, JTAG Test Port Output. Debug and download access.
Ground for GPIO (see Table 78). Typically connected to DGND.
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage
Regulator.
16
16
15
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 µF capacitor to DGND only.
17
18
17
18
16
17
DGND
P0.3/TRST/ADCBUSY
Ground for Core Logic.
General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/
ADCBUSY Signal Output.
19
20
19
20
18
19
RST
Reset Input, Active Low.
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable
Logic Array Output Element 1.
21
21
20
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-
Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable
Logic Array Output Element 2.
Rev. F | Page 23 of 104
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