ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
USB On-The-Go-Dual-Role Device Controller Timing
Table 62 describes the USB On-The-Go Dual-Role Device Con-
troller timing requirements.
Table 62. USB On-The-Go Dual-Role Device Controller Timing Requirements
Parameter
Min
Max
Unit
Timing Requirements
fUSB
USB_XI frequency
9
33.3
+50
MHz
ppm
FSUSB
USB_XI Clock Frequency Stability
–50
JTAG Test And Emulation Port Timing
Table 63 and Figure 60 describe JTAG port operations.
Table 63. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Parameters
tTCK
TCK Period
20
4
ns
ns
ns
ns
ns
tTCK
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
System Inputs Hold After TCK High1
TRST Pulse-Width2 (measured in TCK cycles)
4
4
11
4
Switching Characteristics
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
10
ns
ns
0
16.5
1 System inputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, RESET, NMI, and
BMODE3–0.
2 50 MHz Maximum
3 System outputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0,
DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, CLKOUT, A3–1, and MFS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 60. JTAG Port Timing
Rev. C
|
Page 85 of 100
|
February 2010
ADI [ ADI ]
