ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Ultra DMA Data-Out Transfer Timing
Table 61 and Figure 56 through Figure 59 describes the ATAPI
ultra DMA data-out transfer timing.
Table 61. ATAPI Ultra DMA Data-Out Transfer Timing
ATAPI_ULTRA_TIM_x Timing
ATAPI Parameter
Register Setting1
TDVS, TCYC_TDVS
TDVS, TCYC_TDVS
TDVS
Timing Equation
(TDVS + TCYC_TDVS) × tSCLK
2 × (TDVS + TCYC_TDVS) × tSCLK
TDVS × tSCLK – (tSK1 + tSK2
TCYC_TDVS × tSCLK – (tSK1 + tSK2
TDVS × tSCLK – (tSK1 + tSK2
TACK × tSCLK – (tSK1 + tSK2
TDVS × tSCLK – (tSK1 + tSK2
2
tCYC
t2CYC
tDVS
tDVH
tCVS
Cycle time
Two cycle time
Data valid setup time at sender
Data valid hold time at sender
CRC word valid setup time at host
CRC word valid hold time at host
)
TCYC_TDVS
TDVS
)
)
)
tCVH
tDZFS
TACK
)
Time from data output released-to-driving to first
strobe timing
TDVS
tLI
Limited interlock time
N/A
2 × tBD + 2 × tSCLK + tOD
tMLI
Interlock time with minimum
ATAPI_DMACK to ATAPI_DIOR/DIOW
Ready to final strobe time
TMLI
TENV
N/A
TMLI × tSCLK – (tSK1 + tSK2)
(TENV × tSCLK) +/– (tSK1 + tSK2
2 × tBD + 2 × tSCLK + tOD
3
tENV
)
tRFS
tACK
tSS
Setup and Hold time for ATAPI_DMACK
TACK
TACK × tSCLK – (tSK1 + tSK2
)
Time from STROBE edge to assertion of ATAPI_DIOW TSS
TSS × tSCLK – (tSK1 + tSK2
)
1 ATAPI Timing Register Setting should beprogrammed with a valuethatguarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.
2 ATA/ATAPI-6 compliant functionality with limited speed.
3 This timing equation can be used to calculate both the minimum and maximum tENV
.
Rev. C
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Page 82 of 100
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February 2010
ADI [ ADI ]
