ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Ultra DMA Data-In Transfer Timing
Table 60 and Figure 52 through Figure 55 describe the ATAPI
ultra DMA data-in data transfer timing.
Table 60. ATAPI Ultra DMA Data-In Transfer Timing
ATAPI_ULTRA_TIM_x Timing
ATAPI Parameter
Register Setting1
Timing Equation
TSK3 + tSUDU
tDS
Data setup time at host
N/A
tDH
tCVS
tCVH
tLI
Data hold time at host
N/A
TSK3 + tHDU
CRC word valid setup time at host
CRC word valid hold time at host
Limited interlock time
TDVS
TACK
N/A
TDVS × tSCLK – (tSK1 + tSK2)
TACK × tSCLK – (tSK1 + tSK2
2 × tBD + 2 × tSCLK + tOD
)
tMLI
tAZ
Interlock time with minimum
TZAH, TCVS
N/A
(TZAH + TCVS) × tSCLK – (4 × tBD + 4 × tSCLK + 2 × tOD)
0
Maximum time allowed for output drivers to
release
tZAH
Minimum delay time required for output
ATAPI_DMACK to ATAPI_DIOR/DIOW
ATAPI_DMACK to ATAPI_DIOR/DIOW
Setup and hold times for ATAPI_DMACK
TZAH
TENV
TRP
2 × tSCLK + TZAH × tSCLK + tSCLK
2
tENV
tRP
(TENV × tSCLK) +/- (tSK1 + tSK2
TRP × tSCLK – (tSK1 + tSK2 + tSK4
TACK × tSCLK – (tSK1 + tSK2
)
)
tACK
TACK
)
1 ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.
2 This timing equation can be used to calculate both the minimum and maximum tENV
.
Rev. C
|
Page 79 of 100
|
February 2010
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