ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Enhanced Parallel Peripheral Interface Timing
Table 40 and Figure 32 on Page 60, Figure 30 on Page 59,
Figure 33 on Page 60, and Figure 31 on Page 59 describe
enhanced parallel peripheral interface timing operations.
Table 40. Enhanced Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
PPIx_CLK Width
PPIx_CLK Period
6.0
ns
ns
13.3
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Setup Before PPIx_CLK
External Frame Sync Hold After PPIx_CLK
Receive Data Setup Before PPIx_CLK
Receive Data Hold After PPIx_CLK
0.9
1.9
1.6
1.5
ns
ns
ns
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPIx_CLK
Internal Frame Sync Hold After PPIx_CLK
Transmit Data Delay After PPIx_CLK
Transmit Data Hold After PPIx_CLK
10.5
9.9
ns
ns
ns
ns
2.4
2.4
DATA0 IS
DATA1 IS
SAMPLED
SAMPLED
PPI_CLK
tPCLKW
tSFSPE
tHFSPE
tPCLK
PPI_FS1/2
PPI_DATA
tSDRPE
tHDRPE
Figure 30. EPPI GP Rx Mode with External Frame Sync Timing
DATA DRIVING/
FRAME SYNC
DATA DRIVING/
FRAME SYNC
SAMPLING EDGE
SAMPLING EDGE
PPI_CLK
PPI_FS1/2
PPI_DATA
tSFSPE
tHFSPE
tPCLKW
tPCLK
tDDTPE
tHDTPE
Figure 31. EPPI GP Tx Mode with External Frame Sync Timing
Rev. C
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Page 59 of 100
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February 2010
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