ADSP-21062/ADSP-21062L
JTAG Test Access Port and Emulation
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tTCK
TCK Period
tCK
5
6
7
18
tCK
5
6
7
18.5
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulsewidth
4tCK
4tCK
Switching Characteristics:
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low2
13
18.5
13
18.5
ns
ns
NOTES
1System Inputs = DATA47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, IRQ2-0, FLAG3-0, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2System Outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG3-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. IEEE 11499.1 JTAG Test Access Port
REV. C
–39–
ADI [ ADI ]
