ADSP-21062/ADSP-21062L
Example System Hold Time Calculation
I
OL
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-21062’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
REFERENCE
SIGNAL
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
tMEASURED
tENA
tDIS
Capacitive Loading
V
V
OH (MEASURED)
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 26). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 29–30,
33–34 show how output rise time varies with capacitance. Fig-
ures 31, 35 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 29, 30 and 31 may not be linear outside the ranges
shown.
V
V
OH (MEASURED)
OL (MEASURED)
V
V
– ⌬V
+ ⌬V
2.0V
1.0V
OH (MEASURED)
OL (MEASURED)
OL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 25. Output Enable/Disable
INPUT OR
OUTPUT
1.5V
1.5V
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
REV. C
–41–
ADI [ ADI ]
