ADSP-21062/ADSP-21062L
Synchronous Read/Write—Bus Slave
memory space). The bus master must meet these (bus slave)
timing requirements.
Use these specifications for ADSP-21062 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSADRI
tHADRI
tSRWLI
tHRWLI
tRWHPI
tSDATWH
tHDATWH
Address, SW Setup Before CLKIN
15 + DT/2
15 + DT/2
ns
ns
ns
ns
ns
ns
ns
Address, SW Hold Before CLKIN
RD/WR Low Setup Before CLKIN1
RD/WR Low Hold After CLKIN
RD/WR Pulse High
5 + DT/2
5 + DT/2
9.5 + 5DT/16
–4 – 5DT/16
3
5
1
9.5 + 5DT/16
–4 – 5DT/16
3
5
1
8 + 7DT/16
8 + 7DT/16
Data Setup Before WR High
Data Hold After WR High
Switching Characteristics:
tSDDATO
tDATTR
tDACKAD
tACKTR
Data Delay After CLKIN
19 + 5DT/16
7 – DT/8
9
19 + 5DT/16 ns
Data Disable After CLKIN2
ACK Delay After Address, SW3
ACK Disable After CLKIN3
0 – DT/8
0 – DT/8
7 – DT/8
9
ns
ns
ns
–1 – DT/8
6 – DT/8
–1 – DT/8
6 – DT/8
NOTES
1tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)
= 4 + DT/8.
2See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR
.
REV. C
–24–
ADI [ ADI ]
