ADSP-21062/ADSP-21062L
Memory Read—Bus Master
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Timing Requirements:
tDAD
tDRLD
tHDA
Address, Selects Delay to Data Valid1, 4
18 + DT + W
12 + 5DT/8 + W
18 + DT + W
12 + 5DT/8 + W ns
ns
RD Low to Data Valid1
Data Hold from Address, Selects2
Data Hold from RD High2
0.5
2.0
0.5
2.0
ns
ns
tHDRH
tDAAK
tDSAK
ACK Delay from Address, Selects3, 4
ACK Delay from RD Low3
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W ns
8 + DT/2 + W
ns
Switching Characteristics:
tDRHA
tDARL
tRW
Address, Selects Hold After RD High
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
ns
ns
ns
ns
Address, Selects to RD Low4
RD Pulsewidth
tRWR
RD High to WR, RD, DMAGx Low
tSADADC Address, Selects Setup Before
ADRCLK High4
0 + DT/4
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDATI
.
2Data Hold: User must meet tHDA or tHDRH or synchronous spec tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
3ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
4The falling edge of MSx, SW, BMS is referenced.
ADDRESS
MSx, SW
BMS
tDRHA
tDARL
tRW
RD
tHDA
tHDRH
tDRLD
tDAD
DATA
tDSAK
tRWR
tDAAK
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 13. Memory Read—Bus Master
REV. C
–20–
ADI [ ADI ]
