ADSP-21062/ADSP-21062L
Synchronous Read/Write—Bus Master
When accessing a slave ADSP-21062, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21062 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21062 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSSDATI Data Setup Before CLKIN
tHSDATI Data Hold After CLKIN
3 + DT/8
3.5 – DT/8
3 + DT/8
3.5 – DT/8
ns
ns
tDAAK
ACK Delay After Address, MSx,
SW, BMS1, 2
14 + 7 DT/8 + W
14 + 7 DT/8 + W
ns
ns
ns
tSACKC ACK Setup Before CLKIN2
tHACK
6.5 + DT/4
–1 – DT/4
6.5 + DT/4
–1 – DT/4
ACK Hold After CLKIN
Switching Characteristics:
tDADRO Address, MSx, BMS, SW Delay
After CLKIN1
7 – DT/8
7 – DT/8
ns
tHADRO Address, MSx, BMS, SW Hold
After CLKIN
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16 4 – 3DT/16
8 + DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16 4 – 3DT/16
8 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDPGC
tDRDO
PAGE Delay After CLKIN
RD High Delay After CLKIN
16 + DT/8
4 – DT/8
16 + DT/8
4 – DT/8
tDWRO WR High Delay After CLKIN
tDRWL RD/WR Low Delay After CLKIN
tSDDATO Data Delay After CLKIN
tDATTR Data Disable After CLKIN3
tDADCCK ADRCLK Delay After CLKIN
tADRCK ADRCLK Period
12.5 + DT/4
19 + 5DT/16
7 – DT/8
12.5 + DT/4
19 + 5DT/16
7 – DT/8
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
10 + DT/8
10 + DT/8
tADRCKH ADRCLK Width High
tADRCKL ADRCLK Width Low
W = (number of Wait states specified in WAIT register) × tCK
.
NOTES
1The falling edge of MSx, SW, BMS is referenced.
2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
REV. C
–22–
ADI [ ADI ]
