ADSP-21062/ADSP-21062L
Memory Write—Bus Master
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Timing Requirements:
tDAAK
tDSAK
ACK Delay from Address, Selects1, 2
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W ns
ACK Delay from WR Low1
8 + DT/2 + W
ns
Switching Characteristics:
tDAWH
tDAWL
tWW
tDDWH
tDWHA
Address, Selects to WR Deasserted2
17 + 15DT/16 + W
3 + 3DT/8
17 + 15DT/16 + W
3 + 3DT/8
ns
ns
ns
ns
ns
Address, Selects to WR Low2
WR Pulsewidth
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
Data Setup Before WR High
Address Hold After WR Deasserted
tDATRWH Data Disable After WR Deasserted3
6 + DT/16 + H
6 + DT/16 + H ns
tWWR
tDDWR
tWDE
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
ns
ns
ns
ns
tSADADC Address, Selects to ADRCLK High2
0 + DT/4
0 + DT/4
W = (number of wait states specified in WAIT register) × tCK
.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
2The falling edge of MSx, SW, BMS is referenced.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx , SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD , DMAG
tSADADC
ADRCLK
(OUT)
Figure 14. Memory Write—Bus Master
REV. C
–21–
ADI [ ADI ]
