(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate)
AD9888–SPECIFICATIONS
Test
AD9888KS-100/-1401
AD9888KS-170
AD9888KS-205
Parameter
Temp Level Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
I
VI
I
VI
I
0.5 +1.25/–1.0
+1.35/–1.0
0.6 +1.25/–1.0
+1.50/–1.0
0.75 2.25
2.75
0.8 +1.50/–1.0 LSB
+1.80/–1.0 LSB
Integral Nonlinearity
No Missing Codes
0.5
2.0
2.5
1.0
3.75
4.25
LSB
LSB
25°C
Guaranteed
Guaranteed
Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
25°C
25°C
25°C
I
I
V
0.5
0.5
0.5
V p-p
V p-p
ppm/°C
µA
1.0
1
1.0
1
1.0
1
100
1
100
3
100
1
Input Bias Current
25°C IV
1
2
Full
Full
Full
Full
Full
Full
IV
V
IV
VI
VI
VI
2
2
µA
Input Capacitance
Input Resistance
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
3
3
pF
MΩ
mV
% FS
% FS
7
2.5
49
90
9.0
53
7
2.5
49
90
9.0
53
7
2.5
49
90
9.0
53
44
44
44
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full
Full
VI
V
1.20
1.25 1.30
50
1.20
1.25 1.30
50
1.20
1.25 1.30
50
V
ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
100/140
170
205
MSPS
MSPS
ns
10
+1.25
10
+1.25
10
+1.25
–1.25
4.7
4.0
0
4.7
4.0
250
4.7
4.0
–1.25
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
–1.25
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
2
tBUFF
µs
2
tSTAH
µs
2
tDHO
tDAL
tDAH
tDSU
µs
2
µs
2
µs
2
ns
2
tSTASU
µs
µs
2
tSTOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
15
100/140
110
110
110
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
170
205
10
10
10
25°C IV
Full
Full
470
15
7003
10003
450
15
7004
10004
440
15
7004
10004
IV
IV
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (VIH
Input Voltage, Low (VIL)
)
Full
Full
Full
Full
25°C
VI
VI
IV
IV
V
2.5
2.5
2.5
V
V
µA
µA
pF
0.8
–1.0
+1.0
0.8
–1.0
+1.0
0.8
–1.0
+1.0
Input Current, High (IIH
Input Current, Low (IIL)
Input Capacitance
)
3
3
3
DIGITAL OUTPUTS
Output Voltage, High (VOH
Output Voltage, Low (VOL
Duty Cycle
DATACK, DATACK
Output Coding
)
)
Full
Full
VI
VI
VD – 0.1
44
VD – 0.1
44
VD – 0.1
44
V
V
0.1
55
0
.1
0.1
55
Full
IV
49
49
Binary
55
49
%
Binary
Binary
POWER SUPPLY
VD Supply Voltage
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
IV
IV
IV
V
V
V
VI
VI
VI
3.0
2.2
3.0
3.3
3.3
3.3
200
50
8
850
12
3.6
3.6
3.6
3.0
2.2
3.0
3.3
3.3
3.3
215
55
9
920
12
3.6
3.6
3.6
3.0
2.2
3.0
3.3
3.3
3.3
230
60
10
990
12
3.6
3.6
3.6
V
V
V
mA
mA
mA
mW
mA
mW
V
DD Supply Voltage
PVD Supply Voltage
D Supply Current (VD)
IDD Supply Current (VDD
I
5
)
IPVD Supply Current (PVD
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
)
1050
20
66
1150
20
66
1250
20
66
40
40
40
–2–
REV. A
ADI [ ADI ]
