AD9803
SDATA
SCK
SL
V
DD
0.1F
VOUT2
VOUT1
0.1F
0.1F
0.1F
0.1F
1.0F
48 47 46 45 44 43 42 41 40 39 38 37
V
DD
1
2
3
4
5
6
7
8
9
36
35
34
33
32
NC
ADCIN
D0 (LSB)
D1
AUXCONT
AUXIN
0.1F
ACVDD
D2
0.1F
CLPBYP
D3
ACVSS 31
PGACONT2 30
PGACONT1 29
D4
AD9803
D5
0.1F
0.1F
0.1F
D6
D7
28
27
26
25
CCDBYP1
PIN
10 D8
11 D9 (MSB)
12
CCD
SIGNAL
INPUT
DIN
DIGITAL
OUTPUT
DATA
DRVDD
CCDBYP2
0.1F
13 14 15 16 17 18 19 20 21 22 23 24
V
DD
0.1F
CLPDM
SHD
SHP
CLPOB
PBLK
V
DD
0.1F
NC = NO CONNECT
ADCCLK
Figure 37. CCD-Mode Circuit Configuration—Digital PGA Control
REV. 0
–17–
ADI [ ADI ]
