AD9803
Application Circuit Utilizing the AD9803’s Digital Gain Control
Figure 37 shows the recommended circuit configuration for
CCD-Mode operation when using the 3-wire serial interface.
The analog PGA control pins, PGACONT1 and PGACONT2,
should be shorted together and decoupled to ground. If the two
auxiliary DACs are not used, then Pins 39 and 40 (DAC1 and
DAC2) may be grounded.
NOTE: With the exception of a write to the PGA register dur-
ing AUX-mode, all data writes must be 10 bits. During an
AUX-mode write to the PGA register, only 8 bits of data are
required. If more than 14 SCK rising edges are applied during a
write operation, additional SCK pulses will be ignored (see
Figure 35). All reads must be 10 bits to receive valid register
contents. All registers default to 0s on power-up, except for the
A-register which defaults to 11. Thus, on power-up, the AD9803
defaults to CCD mode. During the power-up phase, it is recom-
mended that SL be HIGH and SCK be LOW to prevent acci-
dental register write operations. SDATA may be unknown. The
RNW bit (“Read/Not Write”) must be LOW for all write opera-
tions to the serial interface, and HIGH when reading back from
the serial interface registers.
Using the AD9803 in AD9801 Sockets
The AD9803 may be easily used in existing AD9801 designs
without any circuit modifications. Most of the pin assignments
are the same for both ICs. Table I outlines the differences. The
circuit of Figure 38 shows the necessary connections for the
AD9803 when used in an existing AD9801 socket. The power-
on reset in the AD9803 assures that the device will power-up in
CCD-mode, with analog PGA gain control.
APPLICATIONS INFORMATION
Power and Grounding Recommendations
Table I. AD9801/AD9803 Pin Differences
Pin
The AD9803 should be treated as an analog component when
used in a system. The same power supply and ground plane
should be used for all of the pins. In a two-ground system, this
requires that the digital supply pins be decoupled to the analog
ground plane and the digital ground pins be connected to ana-
log ground for best noise performance. Separate digital supplies
can be used, particularly if slightly different driver supplies are
needed, but the digital power pins should still be decoupled to
the same point as the digital ground pins (the analog ground
plane). If the AD9803 digital outputs need to drive a bus or
substantial load, then a buffer should be used at the AD9803’s
outputs, with the buffer referenced to system digital ground. In
some cases, when system digital noise is not substantial, it is
acceptable to split the ground pins on the AD9803 to separate
analog and digital ground planes. If this is done, be sure to
connect the two ground planes together at the AD9803.
No.
AD9801
AD9803
AD9801 Connection
1
ADVSS
DSUBST
DVSS
NC
Ground
Ground
Ground
Ground
Decoupled with 0.1 µF
to Ground
+3 Volt Supply
14
15
24
32
DVSS
ACLP
NC
DVSS
CLAMP_BIAS CLPBYP
34
35
36
ACVDD
ACVDD
INT_BIAS1
AUXIN
AUXCONT +3 Volt Supply
ADCIN
Decoupled with 0.1 µF
to Ground
Decoupled with 0.1 µF
to Ground
Ground
Ground
Ground
38
INT_BIAS2
VTRBYP
39
40
41
42
44
MODE2
MODE1
ADVSS
ADVDD
ADVSS
DAC1
DAC2
SL
SCK
SDATA
To further improve performance, isolating the driver supply
DRVDD from DVDD with a ferrite bead can help reduce kick-
back effects during major code transitions. Alternatively, the
use of damping resistors on the digital outputs will reduce the
output rise times, also reducing the kickback effect.
+3 Volt Supply
Ground
–16–
REV. 0
ADI [ ADI ]
