AD9803
REGISTER DESCRIPTION
(a) A-REGISTER: Modes of Operation (Power-On Default
Value = 11)
(f) F-REGISTER: PGA Gain Selection (Default = 00 . . . 0)
f9 f8 f7 f6 f5 f4 f3 f2
AUX-Gain
a1
a0
Modes
Gain (0)
Gain (255)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Minimum
Maximum
0
0
1
1
0
1
0
1
ADC-MODE
AUX-MODE
CCD-MODE
CCD-MODE
(g) G-REGISTER: DAC1 Input (Default = 00 . . . 0)
g7 g6 g5 g4 g3 g2 g1 g0 DAC1 Output
(b) B-REGISTER: Output Modes (Default = 00)
Code (0)
Code (255) 1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Minimum
Maximum
b1 b0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
Normal
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
(h) H-REGISTER: DAC2 Input (Default = 00 . . . 0)
h7 h6 h5 h4 h3 h2 h1 h0 DAC2 Output
High Impedance
Code (0)
Code (255) 1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Minimum
Maximum
(c) C-REGISTER: Clock Modes (Default = 00)
c1 c0
SHP-SHD Clock Pulses
Clamp Active Pulses
(j) J-REGISTER: Even-Odd Offset Correction (Default = 0)
0
0
1
1
0
1
0
1
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
j0
Even-Odd Offset Correction
0
1
Offset Correction In Use
Offset Correction Not Used
(d) D-REGISTER: Power-Down Modes (Default = 00)
(k) K-REGISTER: External PGA Gain Control (Default = 0)
Modes
d1
d0 Description
k0
PGA Gain Control
Normal
High Speed
Power-Down 1
0
0
1
0
1
0
Normal Operation
0
External Voltage Control Through AUXCONT or
PGACONT1 and PGACONT2
High Speed AUX-MODE
Reference Stand-By (Same Mode
as STBY Pin 18)
1
Internal 10-Bit DAC Control of PGA Gain
Power-Down 2
1
1
Total Shut-Down
(m) M-REGISTER: DAC1 & DAC2 pdn (Default = 0)
(e) E-REGISTER: Clamp Level Selection (Default = 00)
m0
Power-Down of 8-Bit DACs
e1
e0
Clamp Level
0
1
8-Bit DACs Powered-Down
8-Bit DACs Operational
CLP (0)
CLP (1)
CLP (2)
CLP (3)
0
0
1
1
0
1
0
1
32 LSBs
48 LSBs
64 LSBs
16 LSBs
(f) F-REGISTER: PGA Gain Selection (Default = 00 . . . 0)
f9 f8 f7 f6 f5 f4 f3 f2 f1 f0
CCD-Gain
Gain (0)
Gain (1023) 1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Minimum
Maximum
REV. 0
–15–
ADI [ ADI ]
