AD9803
Black Level Clamping
CLPDM
For correct signal processing, the CCD signal must be refer-
enced to a well established “black level.” The AD9803 uses the
CCD’s optical black (OB) pixels as a calibration signal, which is
used to establish the black level. Two sources of offset are
addressed during the calibration—the CCD’s own “black level”
offset, and the AD9803’s internal offsets in the CDS and PGA
circuitry.
INPUT
CLAMP
CCD
PGA
TO ADC
CDS
BLACK
LEVEL CLP
The feedback loop shown in Figure 28 is closed around the
PGA during the calibration interval (CLPOB = LOW) to set
the black level. As the black pixels are being processed, an inte-
grator block measures the difference between the input level
and the desired reference level. This difference, or error, signal
is amplified and passed to the CDS block where it is added to
the incoming pixel data. As a result of this process, the black
pixels are digitized at one end of the ADC range, taking maxi-
mum advantage of the available linear range of the system.
Using the AD9803’s serial digital interface, the black level
reference may programmed to 16 LSB, 32 LSB, 48 LSB, or
64 LSB.
Figure 30. Input Clamp
Input Blanking
In some applications, the AD9803’s input may be exposed to
large signals from the CCD, either during blanking intervals or
“high speed” modes. If the signals are larger than the AD9803’s
1 V p-p input signal range, then the on-chip input circuitry
may saturate. Recovery time from a saturated state could be
substantial.
To avoid problems associated with processing these large tran-
sients, the AD9803 includes an input blanking function. When
active (PBLK = LOW) this function stops the CDS operation
and allows the user to disconnect the CDS inputs from the
CCD buffer. Additionally, the AD9803’s digital outputs will all
go to zero while PBLK is low.
IN
CDS
ADC
PGA
CLPOB
If the input voltage exceeds the supply rail by more than
0.3 volts, then protection diodes will be turned on, increasing
current flow into the AD9803 (see Equivalent Input Circuits).
Such voltage levels should be externally clamped to prevent
possible device damage.
INTEGRATOR
NEG REF
Figure 28. Black Level Correction Loop (Simplified)
The actual implementation of this loop is slightly more compli-
cated as shown in Figure 29. Because there are two separate
CDS blocks, two black level feedback loops are required and
two offset voltages are developed. Figure 29 also shows an
additional PGA block in the feedback loop labeled “RPGA.”
The RPGA uses the same control inputs as the PGA, but has
the inverse gain. The RPGA functions to attenuate by the same
factor as the PGA amplifies, keeping the gain and bandwidth of
the loop constant.
10-Bit Analog-to-Digital Converter (ADC)
The ADC employs a multibit pipelined architecture which is
well-suited for high throughput rates while being both area and
power efficient. The multistep pipeline presents a low input
capacitance resulting in lower on-chip drive requirements. A
fully differential implementation was used to overcome head-
room constraints of the single +3 V power supply.
There exists an unavoidable mismatch in the two offset voltages
used to correct both CDS blocks. This mismatch causes a
slight difference in the offset level for odd and even pixels, often
called “pixel-to-pixel offset” or “even-odd offset.” To compen-
sate for this mismatch, the AD9803 uses a digital correction
circuit after the ADC which removes the even-odd offset be-
tween the channels.
Differential Reference
The AD9803 includes a 0.5 V reference based on a differential,
continuous-time bandgap cell. Use of an external bypass capaci-
tor reduces the reference drive requirements, thus lowering the
power dissipation. The differential architecture was chosen for
its ability to reject supply and substrate noise. Required decou-
pling is shown in Figure 31.
0.1F
CDS1
VRT
IN
PGA
ADC
1F
REF
VRB
CDS2
CLPOB
0.1F
INT2
INT1
RPGA2
RPGA1
Figure 31. Reference Decoupling
Internal Timing
NEG REF
CONTROL
The AD9803’s on-chip timing circuitry generates all clocks
necessary for operation of the CDS and ADC blocks. The user
needs only to synchronize the SHP and SHD clocks with the
CCD waveform, as all other timing is handled internally. The
ADCCLK signal is used to strobe the output data, and can be
adjusted to accommodate desired timing. Figure 1 shows the
recommended placement of ADCCLK relative to SHP and
SHD.
Figure 29. Black Level Correction Loop (Detailed)
Input Bias Level Clamping
The buffered CCD output is connected to the AD9803 through
an external coupling capacitor. The dc bias point for this cou-
pling capacitor is established during the clamping (CLPDM =
LOW) period using the “dummy clamp” loop shown in Figure
30. When closed around the CDS, this loop establishes the
desired dc bias point on the coupling capacitor.
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REV. 0
ADI [ ADI ]
