AD9803
Even-Odd Pixel Offset Correction
The recommended method of controlling the input clamp is
to simply ground the ACLP input (Pin 15) to activate the
“automatic” clamping capability of the AD9803. The clamp
may also be controlled with a separate clock signal. See the
clamp timing in Figure 4 for more details.
The AD9803 includes digital correction circuitry following the
10-bit ADC. The purpose of the digital correction is remove
the residual offset between the even and odd pixel channels,
which results from the “ping-pong” CDS architecture of the
AD9803. The digital offset correction tracks the black level of
the even and odd channels, applying the necessary digital cor-
rection value to keep them balanced. There is an additional two
cycle delay when using the offset correction, resulting in pipe-
line delay of 7 ADCCLK cycles (see Figure 1).
The THD performance for fS = 18 MHz is shown in Figure 21.
When operating at fS = 18 MHz, the linearity performance is
comparable to the CCD-Mode linearity, shown in Figure 18.
The AUX-MODE can be operated at a sampling rate of up to
28.6 MHz. If the sample rate exceeds 18 MHz, then the High
Speed AUX-MODE should be programmed through the serial
interface (D-Register 01).
ADCCLK
A/D
CONVERTER
EVEN
10
2:1
MUX
AD9803
DOUT
0~10 dB
AUXIN
VIDEO
+
ODD
34
ADC
PGA
SHA
LPF
SIGNAL
0.1F
CLPOB
2A
DIGITAL
OFFSET
CORRECTION
–
CLP
+
CLAMP LEVEL (E-REG)
Figure 32. Digital Offset Correction
Auxiliary DACs
35
16
15
AUX
CONT
ACLP
0.1F
ADCCLK
The AD9803 includes two 8-bit DACs for controlling any off-
chip system functions. These are voltage output DACs with
near rail-to-rail output capability. Output voltage levels are
programmed through the serial interface. DAC specifications
are shown on page 4, and the DAC equivalent output circuit is
shown in Figure 14.
GND
Figure 33. AUX-MODE Circuit Configuration
ADC-MODE Operation
The ADC-MODE of operation is the same as the AUX-MODE,
except there is no PGA in the signal path, only the input clamp
and ADC. Input specifications and timing for ADC-MODE are
the same as those for AUX-MODE. The THD performance is
shown in Figure 22.
AUX-MODE Operation
In addition to the CCD signal-processing path, the AD9803
includes an analog video-processing path. The AUXIN (Pin 34)
input consists of an input clamp, PGA, and ADC. Figure 33
shows the Input Configuration of this mode. The recommended
value of the external ac-coupling capacitor is 0.1 µF. The volt-
age droop with this capacitor value is 20 µV/µs.
REV. 0
–13–
ADI [ ADI ]
