AD9803
SERIAL INTERFACE SPECIFICATIONS
SDATA
A1
0
A2
0
A0
1
D0
e0
D1
e1
D2
d0
D3
d1
D4
c0
D5
c1
D6
b0
D7
b1
D8
a0
D9
a1
SELECT
MODES
CLAMP
LEVEL
POWER DOWN
MODES
CLOCK
MODES
OUTPUT
MODES
OPERATION
MODES
f0
f1
f2
f3
f4
f5
f6
f7
f8
f9
PGA
DAC1
DAC2
0
1
0
PGA GAIN LEVEL SELECTION
g0
g1
g2
g3
g4
g5
h5
g6
h6
g7
1
0
1
1
0
0
1
1
DAC1 INPUT
h0
h1
0
h2
k0
h3
h4
h7
DAC2 INPUT
m0
j0
MODES21
1
OPERATION AND
POWER DOWN MODES
NOTE
1MODES2 REGISTER BIT D1 MUST
BE SET TO ZERO.
SELECT
SHIFT REGISTER
a0–a1
A-REG
b0–b1
B-REG
c0–c1
C-REG
d0–d1
D-REG
e0–e1
f0–f9
E-REG
F-REG
(a) OPERATION MODES
g0–g7
(b) OUTPUT MODES
h0–h7
(c) CLOCK MODES
j0
(d) POWER DOWN MODES
k0
(e) CLAMP LEVEL
(f) PGA GAIN
m0
H-REG
J-REG
K-REG
M-REG
G-REG
(g) DAC1 INPUT
(h) DAC2 INPUT
(j) EVEN-ODD OFFSET
CORRECTION
(k) EXTERNAL PGA
GAIN CONTROL
(m) DAC1 AND DAC2
POWER DOWN
Figure 34. Internal Register Map
RNW
D4
SDATA
A0
A1
A2
D0
D1
D2
D3
D5
D6
D7
D8
D9
RISING EDGE
TRIGGERED
tDS
tDH
SCK
SL
tLS
tLH
REGISTER LOADED ON
RISING EDGE
Figure 35. Serial WRITE Operation
DUMMY BITS
IGNORED
RNW
SDATA
A0
A1
A2
D0
D1
D2
D3
D5
D6
D7
D8
D9
XX
XX
D4
SCK
SL
Figure 36. 16-Bit Serial WRITE Operation
–14–
REV. 0
ADI [ ADI ]
