Data Sheet
AD9364
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
Bus Turnaround Time
Before Rx
tRPRE
tRPST
2 × tCP
ns
ns
pF
pF
After Rx
2 × tCP
Capacitive Load
Capacitive Input
SUPPLY CHARACTERISTICS
1.3 V Main Supply Voltage
3
3
1.267
1.3
1.33
V
VDD_INTERFACE Supply
Nominal Settings
CMOS
1.2
1.8
−5
2.5
2.5
+5
V
LVDS
V
VDD_INTERFACE Tolerance
%
Tolerance is applicable to
any voltage setting
VDD_GPO Supply Nominal
Setting
1.3
−5
3.3
+5
V
When unused, must be set
to 1.3 V
VDD_GPO Tolerance
%
Tolerance is applicable to
any voltage setting
Current Consumption
VDDx, Sleep Mode
VDD_GPO
180
50
μA
μA
Sum of all input currents
No load
1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
CURRENT CONSUMPTION—VDD_INTERFACE
Table 2. VDD_INTERFACE = 1.2 V
Parameter
Min
Min
Min
Typ
Max
Max
Max
Unit
Test Conditions/Comments
SLEEP MODE
45
μA
Power applied, device disabled
RX AND TX, DOUBLE DATA RATE (DDR)
LTE 10 MHz
Single Port
Dual Port
LTE 20 MHz
Dual Port
2.9
2.7
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
5.2
mA
30.72 MHz data clock, CMOS
Table 3. VDD_INTERFACE = 1.8 V
Parameter
SLEEP MODE
Typ
Unit
Test Conditions/Comments
84
μA
Power applied, device disabled
RX AND TX, DDR
LTE 10 MHz
Single Port
Dual Port
LTE 20 MHz
Dual Port
4.5
4.1
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
8.0
mA
30.72 MHz data clock, CMOS
Table 4. VDD_INTERFACE = 2.5 V
Parameter
Typ
Unit
Test Conditions/Comments
SLEEP MODE
150
μA
Power applied, device disabled
RX AND TX, DDR
LTE 10 MHz
Single Port
Dual Port
6.5
6.0
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
LTE 20 MHz
Dual Port
11.5
mA
30.72 MHz data clock, CMOS
Rev. B | Page 7 of 32
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