Data Sheet
AD9364
Parameter1
Output Voltage
Minimum
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
0.5
V
Maximum
VDD_GPO − 0.3
10
V
Output Current
DIGITAL SPECIFICATIONS (CMOS)
Logic Inputs
Input Voltage
High
mA
VDD_INTERFACE × 0.8
VDD_INTERFACE
V
V
Low
0
VDD_INTERFACE × 0.2
Input Current
High
−10
−10
+10
+10
μA
μA
Low
Logic Outputs
Output Voltage
High
VDD_INTERFACE × 0.8
V
V
Low
VDD_INTERFACE × 0.2
DIGITAL SPECIFICATIONS (LVDS)
Logic Inputs
Input Voltage Range
825
1575
+100
mV
mV
Ω
Each differential input in the
pair
Input Differential Voltage
Threshold
−100
Receiver Differential Input
Impedance
100
Logic Outputs
Output Voltage
High
1375
mV
mV
mV
Low
1025
150
Output Differential Voltage
Programmable in 75 mV
steps
Output Offset Voltage
GENERAL-PURPOSE OUTPUTS
Output Voltage
High
1200
10
mV
VDD_GPO × 0.8
V
Low
VDD_GPO × 0.2
V
Output Current
SPI TIMING
mA
VDD_INTERFACE = 1.8 V
SPI_CLK
Period
tCP
20
9
ns
ns
ns
Pulse Width
tMP
SPI_ENB Setup to First SPI_CLK tSC
Rising Edge
1
Last SPI_CLK Falling Edge to
SPI_ENB Hold
tHC
0
ns
SPI_DI
Data Input Setup to
SPI_CLK
tS
2
1
ns
ns
Data Input Hold to SPI_CLK
tH
SPI_CLK Rising Edge to Output
Data Delay
4-Wire Mode
tCO
3
8
ns
ns
ns
3-Wire Mode
tCO
3
8
Bus Turnaround Time, Read
tHZM
tH
tCO (max)
After baseband processor
(BBP) drives the last address
bit
Bus Turnaround Time, Read
tHZS
0
tCO (max)
ns
After the AD9364 drives the
last data bit
Rev. B | Page 5 of 32
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