AD9364
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK Clock Period
tCP
16.276
ns
ns
61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
Tx Data
TX_FRAME, P0_D, and P1_D
Setup to FB_CLK
Hold to FB_CLK
tSTX
tHTX
1
0
0
ns
ns
ns
DATA_CLK to Data Bus Output tDDRX
Delay
1.5
1.0
DATA_CLK to RX_FRAME
Delay
tDDDV
0
ns
Pulse Width
ENABLE
tENPW
tCP
tCP
ns
ns
TXNRX
tTXNRXPW
FDD independent ENSM
mode
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
tTXNRXSU
0
ns
TDD ENSM mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
TDD mode
TDD mode
After Rx
Capacitive Load
Capacitive Input
3
3
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK Clock Period
tCP
16.276
ns
ns
61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
Tx Data
TX_FRAME, P0_D, and P1_D
Setup to FB_CLK
Hold to FB_CLK
tSTX
tHTX
1
0
0
ns
ns
ns
DATA_CLK to Data Bus Output tDDRX
Delay
1.2
1.0
DATA_CLK to RX_FRAME
Delay
tDDDV
0
ns
Pulse Width
ENABLE
tENPW
tCP
tCP
ns
ns
TXNRX
tTXNRXPW
FDD independent ENSM
mode
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
tTXNRXSU
0
ns
TDD ENSM mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
TDD mode
TDD mode
After Rx
Capacitive Load
3
3
Capacitive Input
DIGITAL DATA TIMING (LVDS)
DATA_CLK Clock Period
tCP
4.069
ns
ns
245.76 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
Tx Data
TX_FRAME and TX_D
Setup to FB_CLK
Hold to FB_CLK
tSTX
tHTX
1
ns
ns
ns
0
DATA_CLK to Data Bus Output tDDRX
Delay
0.25
1.25
1.25
DATA_CLK to RX_FRAME
Delay
tDDDV
0.25
ns
Pulse Width
ENABLE
tENPW
tCP
tCP
ns
ns
TXNRX
tTXNRXPW
FDD independent ENSM
mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ENSM mode
Rev. B | Page 6 of 32
ADI [ ADI ]
