AD8325
(DATEN, CLK, SDATA, TXEN, SLEEP, V = 5 V: Full Temperature Range)
LOGIC INPUTS (TTL/CMOS-Compatible Logic)
CC
Parameter
Min
Typ
Max
Unit
Logic “1” Voltage
Logic “0” Voltage
2.1
0
5.0
0.8
V
V
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
Logic “1” Current (VINH = 5 V) TXEN
Logic “0” Current (VINL = 0 V) TXEN
Logic “1” Current (VINH = 5 V) SLEEP
Logic “0” Current (VINL = 0 V) SLEEP
0
–600
50
–250
50
–250
20
nA
nA
µA
µA
µA
µA
–100
190
–30
190
–30
TIMING REQUIREMENTS
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (TWH
Clock Period (TC)
Setup Time SDATA vs. Clock (TDS
Setup Time DATEN vs. Clock (TES
Hold Time SDATA vs. Clock (TDH
Hold Time DATEN vs. Clock (TEH
Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)
)
16.0
32.0
5.0
15.0
5.0
ns
ns
ns
ns
ns
ns
ns
)
)
)
)
3.0
10
T
DS
VALID DATA WORD G1
VALID DATA WORD G2
SDATA
MSB. . . .LSB
T
C
T
WH
CLK
T
T
EH
ES
8 CLOCK
CYCLES
DATEN
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
T
OFF
TXEN
T
GS
T
ON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB-1
MSB
SDATA
CLK
MSB-2
T
T
DH
DS
Figure 3. SDATA Timing
–3–
REV. 0
ADI [ ADI ]
