AD8132
offset values in the Specifications section assume the VOCM input
is driven by a low impedance voltage source.
When using the AD8132 in gain configurations where β1 ≠ β2,
differential output noise appears due to input-referred voltage
noise in the VOCM circuitry according to the following formula:
DRIVING A CAPACITIVE LOAD
⎡
⎢
⎤
⎥
β1 − β2
β1 + β2
A purely capacitive load can react with the pin and bond wire
inductance of the AD8132, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance must be small to avoid destabilizing the amplifier. An
alternative technique is to place a small resistor in series with
the amplifier outputs, as shown in Figure 60.
VOND = 2 VNOCM
⎢
⎣
⎥
⎦
where VOND is the output differential noise and VNOCM is the
input-referred voltage noise on VOCM
.
CALCULATING INPUT IMPEDANCE OF THE
APPLICATION CIRCUIT
OPEN-LOOP GAIN AND PHASE
The effective input impedance of a circuit, such as that in Figure 64,
at +DIN and −DIN, depends on whether the amplifier is being driven
by a single-ended or differential signal source. For balanced differ-
ential input signals, the input impedance (RIN, dm) between the
inputs (+DIN and −DIN) is simply
Open-loop gain and phase plots are shown in Figure 65 and
Figure 66.
60
R
= 2kΩ
L, dm
50
40
30
RIN,dm = 2 × RG
In the case of a single-ended input signal (for example, if −DIN
is grounded and the input signal is applied to +DIN), the input
impedance becomes
20
10
0
⎛
⎜
⎞
⎟
RG
RF
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
RIN,dm
=
1 −
–10
–20
2 ×
(
RG + RF
)
0.1
1
10
100
1000
The circuit input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the Input Resistor RG.
FREQUENCY (MHz)
Figure 65. Open-Loop Gain Plot
40
20
R
= 2kΩ
L, dm
0
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
–20
–40
–60
–80
–100
The AD8132 is optimized for level-shifting ground-referenced
input signals. For a single-ended input, this implies that the voltage
at −DIN in Figure 64 is 0 V when the amplifier’s negative power
supply voltage (at V−) was also set to 0 V.
–120
–140
–160
SETTING THE OUTPUT COMMON-MODE VOLTAGE
–180
–200
The AD8132s VOCM pin is internally biased at a voltage approx-
imately equal to the midsupply point (average value of the voltage
on V+ and V−). Relying on this internal bias results in an output
common-mode voltage that is within approximately 100 mV
of the expected value.
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 66. Open-Loop Phase Plot
In cases where more accurate control of the output common-mode
level is required, it is best practice that an external source or resistor
divider (with RSOURCE < 10 kΩ) be used. The output common-mode
Rev. F | Page 23 of 32
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