Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 V
BAT
15 GND
14 Y–
13 X–
AD7873
AUX 1
V
REF
2
+V
CC
3
PENIRQ 4
12 Y+
AD7873
TOP VIEW
11 X+
10 +V
CC
9
DCLK
+V
CC
X+
Y+
1
2
3
4
5
6
7
8
16
DCLK
15
CS
14
DIN
DOUT 5
BUSY 6
DIN 7
CS 8
X–
Y–
GND
V
BAT
02164-003
AD7873
TOP VIEW
(Not to Scale)
13
BUSY
12
DOUT
11
PENIRQ
10
+V
CC
9
AUX
V
REF
Figure 3. LFCSP Pin Configuration
Figure 4. QSOP/TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
QSOP/
LFCSP
TSSOP
3, 10
1, 10
11
12
13
14
15
16
1
2
2
3
4
5
6
7
8
9
Mnemonic
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
V
REF
Description
Power Supply Input. The +V
CC
range for the AD7873 is from 2.2 V to 5.25 V. Both +V
CC
pins should be
connected directly together.
X+ Position Input. ADC Input Channel 1.
Y+ Position Input. ADC Input Channel 2.
X– Position Input.
Y– Position Input. ADC Input Channel 3.
Analog Ground. Ground reference point for all circuitry on the AD7873. All analog input signals
and any external reference signals should be referred to this GND voltage.
Battery Monitor Input. ADC Input Channel 4.
Auxiliary Input. ADC Input Channel 5.
Reference Output for the AD7873. Alternatively, an external reference can be applied to this input.
The voltage range for the external reference is 1.0 V to +V
CC
. For specified performance, it is 2.5 V on
the AD7873. The internal 2.5 V reference is available on this pin for use external to the device. The
reference output must be buffered before it is applied elsewhere in a system. A 0.1 µF capacitor is
recommended between this pin and GND to reduce system noise effects.
Pen Interrupt. CMOS logic open-drain output (requires 10 kΩ to 100 kΩ pull-up resistor externally).
Data Out. Logic output. The conversion result from the AD7873 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is
high impedance when CS is high.
BUSY Output. Logic output. This output is high impedance when CS is high.
Data In. Logic Input. Data to be written to the AD7873 control register is provided on this input and
is clocked into the register on the rising edge of DCLK (see the Control Register section).
Chip Select Input. Active low logic input. This input provides the dual function of initiating
conversions on the AD7873 and enabling the serial input/output register.
External Clock Input. Logic input. DCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7873 conversion process.
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder
joints and maximum thermal capability, it is recommended that the pad be soldered to the ground
plane.
4
5
11
12
PENIRQ
DOUT
6
7
8
9
13
14
15
16
N/A
BUSY
DIN
CS
DCLK
EPAD
1
N/A = not applicable.
Rev. F | Page 7 of 28
02164-004
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED
TO GROUND PLANE.
AD [ ANALOG DEVICES ]
