AD5382
MICROPROCESSOR INTERFACING
Parallel Interface
The AD5382 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 35 shows the AD5382 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0–A4 on the AD5382. The upper address lines are decoded to
provide a CS, LDAC
signal
for the AD5382. The fast interface
timing of the AD5382 allows direct interface to a wide variety of
microcontrollers and DSPs, as shown in Figure 35.
being transmitted to the AD5382, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle.
MC68HC11
DV
DD
AD5382
SER/PAR
RESET
AD5382 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5382, the MOSI output drives the serial data line (D
IN
)
of the AD5382, and the MISO input is driven from D
OUT
. The
SYNC signal is derived from a port line (PC7). When data is
MISO
MOSI
SCK
PC7
SDO
DIN
SCLK
SYNC
SPI/I2C
03733-0-004
Figure 34. AD5382-to-MC68HC11 Interface
µCONTROLLER/
DSP PROCESSOR*
AD5382
D15
DATA
BUS
D0
UPPER BITS OF
ADDRESS BUS
ADDRESS
DECODE
REG1
REG0
D13
D0
CS
LDAC
A4
A3
A2
A1
A0
R/W
A4
A3
A2
A1
A0
WR
03733-0-005
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. AD5382-to-Parallel Interface
Rev. 0 | Page 31 of 40
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