AD5382
Daisy-Chain Mode
Readback Mode
Readback mode is invoked by setting the R/ bit = 1 in the
serial input register write. With R/ = 1, Bits A4 to A0, in
W
For systems that contain several devices, the SDO pin may be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
W
association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output will contain the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO. Figure 30 shows the readback sequence. For example, to
read back the M register of channel 0 on the AD5382, the
following sequence should be implemented. First, write
0x404XXX to the AD5382 input register. This configures the
AD5382 for read mode with the m register of Channel 0
selected. Note that data bits DB13 to DB0 are don’t cares. Follow
this with a second write, a NOP condition, 0x000000. During
this write, the data from the m register is clocked out on the
DOUT line, i.e., data clocked out will contain the data from the
m register in Bits DB13 to DB0, and the top 10 bits contain the
address information as previously written. In readback mode,
the SYNC signal must frame the data. Data is clocked out on the
rising edge of SCLK and is valid on the falling edge of the SCLK
signal. If the SCLK idles high between the write and read
operations of a readback operation, the first bit of data is
By connecting the DCEN (Daisy-Chain Enable) pin high, daisy-
chain mode is enabled. The first falling edge of
starts the
SYNC
write cycle. The SCLK is continuously applied to the input shift
register when is low. If more than 24 clock pulses are
SYNC
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO of
the first device to the DIN input on the next device in the chain,
a multidevice interface is constructed. Twenty-four clock pulses
are required for each device in the system. Therefore, the total
number of clock cycles must equal 24N, where N is the total
number of AD538x devices in the chain.
When the serial transfer to all devices is complete,
is
SYNC
taken high. This latches the input data in each device in the
daisy-chain and prevents any further data from being clocked
into the input shift register.
If the SYNC is taken high before 24 clocks are clocked into the
part, this is considered a bad frame and the data is discarded.
clocked out on the falling edge of
.
SYNC
The serial clock may be either a continuous or a gated clock. A
continuous SCLK source can only be used if it can be arranged
that
is held low for the correct number of clock cycles. In
SYNC
gated clock mode, a burst clock containing the exact number of
clock cycles must be used and
must be taken high after
SYNC
the final clock to latch the data.
SCLK
SYNC
24
48
DB23
DB0
DB23
DB0
DIN
INPUT WORD SPECIFIES REGISTER TO BE READ
NOP CONDITION
DB23
DB0
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 30. Serial Readback Operation
Rev. 0 | Page 27 of 40
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