AD1847
Control Word (16-Bit)
Data 15
CLOR
Data 7
DATA7
Data 14
MCE
Data 6
DATA6
Data 13
RREQ
Data 5
DATA5
Data 12
res
Data 4
DATA4
Data 11
IA3
Data 3
DATA3
Data 10
IA2
Data 2
DATA2
Data 9
IA1
Data 1
DATA1
Data 8
IA0
Data 0
DATA0
DATA7:0 Index Register Data. These bits are the data for the desired AD1847 Index Register referenced by the Index Address.
Written by the host CPU or DSP to the AD1847.
IA3:0
RREQ
Index Register Address. These bits define the indirect address of the desired AD1847 Index Register. Written by the host
CPU or DSP to the AD1847.
Read Request. Setting this bit indicates that the current transfer is a request by the host CPU or DSP for readback of the
contents of the indirect addressed Index Register. When this bit is set (RREQ = HI), the AD1847 will not transmit its
Status Word in the following Status Word Index readback slot, but will instead transmit the data in the Index Register
specified by the Index Address. Although the Index Readback is transmitted in the following Status Word/Index
Readback time slot, the format of the Control Word is used (i.e., CLOR, MCE, RREQ and the Index Register Address
in the most significant byte, and the readback Index Register Data in the least significant byte). When this bit is reset
(RREQ = LO), the AD1847 will transmit its Status Word in the following Status Word Index Readback time slot.
A read request is serviced in the next available Index Readback time slot. If TSSEL = 0, the Index Register readback
data is transmitted in slot 3 of the same sample. If TSSEL = 1, Index Register readback data is transmitted in slot 0 of
the next sample. If TSSEL changes from 0 to 1, Index Register readback will occur twice, in slot 3 of the current sample,
and slot 0 of the next. If TSSEL changes from 1 to 0, the last read request is lost.
res
MCE
Reserved for future expansion. Write zeros (LO) to all reserved bits.
Mode Change Enable. This bit must be set (MCE = HI) whenever protected control register bits of the AD1847 are
changed. The Data Format register, the Miscellaneous Information register, and the ACAL bit of the Interface Configu-
ration register can NOT be changed unless this bit is set. The DAC outputs will be muted when MCE is set. The user
must mute the AUX1 and AUX2 channels when this bit is set (no audio activity should occur). Written by the host CPU
or DSP to the AD1847. This bit is HI after reset.
Clear Overrange. When this bit is set (CLOR = HI), the overrange bits in the Status Word are updated every sample.
When this bit is reset (CLOR = LO), the overrange bits in the Status Word will record the largest overrange value. The
largest overrange value is sticky until the CLOR bit is set. Written by the host CPU or DSP to the AD1847. Since there
can be up to 2 samples in the data pipeline, a change to CLOR may take up to 2 samples periods to take effect. This bit
is HI after reset.
CLOR
Immediately after reset, the contents of this register is: 1100 0000 0000 0000 (C000h).
Left/Right Playback/Capture Data (16-Bit)
The data formats for Left Playback, Right Playback, Left Capture and Right Capture are all identical.
Data 15
DATA15
Data 7
DATA7
Data 14
DATA14
Data 6
DATA6
Data 13
DATA13
Data 5
DATA5
Data 12
DATA12
Data 4
DATA4
Data 11
DATA11
Data 3
DATA3
Data 10
DATA10
Data 2
DATA2
Data 9
DATA9
Data 1
DATA1
Data 8
DATA8
Data 0
DATA0
DATA15:0 Data Bits. These registers contain the 16-bit, MSB first data for capture and playback. The host CPU or DSP reads the
capture data from the AD1847. The host CPU or DSP writes the playback data to the AD1847. For 8-bit linear or 8-bit
companded modes, only DATA15:8 contain valid data; DATA7:0 are ignored during capture, and are zeroed during
playback. Mono mode plays back the same audio sample on both left and right channels. Mono capture only captures
data from the left audio channel. See “Serial Data Format” Timing Diagram.
Immediately after reset, the content of these registers is: 0000 0000 0000 0000 (0000h).
–10–
REV. B
AD [ ANALOG DEVICES ]
