AD1846
PIN DESCRIPTION
Parallel Interface
Pin Name
CDRQ
PLCC
12
I/O
O
Description
Capture Data Request. The assertion of this signal indicates that the Codec has a captured
audio sample from the ADC ready for transfer. This signal will remain asserted until all the
bytes from the capture buffer have been transferred.
Capture Data Acknowledge. The assertion of this active LO signal indicates that the
RD
cycle occurring is a DMA read from the capture buffer.
Playback Data Request. The assertion of this signal indicates that the Codec is ready for
more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.
Playback Data Acknowledge. The assertion of this active LO signal indicates that the
WR
cycle occurring is a DMA write to the playback buffer.
Codec Addresses. These address pins are asserted by the Codec interface logic during a con-
trol register/PIO access. The state of these address lines determine which register is accessed.
Read Command Strobe. This active LO signal defines a read cycle from the Codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.
Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the Codec’s
DMA sample registers.
AD1846 Chip Select. The Codec will not respond to any control/PIO cycle accesses unless
this active LO signal is LO. This signal is ignored during DMA transfers.
Data Bus. These pins transfer data and control information between the Codec and the host.
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN
= (WR OR
RD)
AND
CS
For DMA cycles,
DBEN
= (WR OR
RD)
AND (PDAK OR
CDAK)
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI enables
writes from the host to the AD1846; LO enables reads from the AD1846 to the host bus.
This signal is normally HI.
For control register/PIO cycles,
DBDIR =
RD
AND
CS
For DMA cycles,
DBDIR =
RD
AND (PDAK OR
CDAK)
CDAK
PDRQ
11
14
I
O
PDAK
ADR1:0
RD
13
9 & 10
60
I
I
I
WR
61
I
CS
DATA7:0
DBEN
59
3–6 &
65–68
63
I
I/O
O
DBDIR
62
O
REV. A
–7–
AD [ ANALOG DEVICES ]
