AD14060/AD14060L
Asynchr onous Read/Wr ite—H ost to AD 14060/AD 14060L
Use these specifications for asynchronous host processor accesses
of an AD14060/AD14060L, after the host has asserted CS and
HBR (low). After HBG is returned by the AD14060/
AD14060L, the host can drive the RD and WR pins to access
the AD14060/AD14060L’s internal memory or IOP registers.
HBR and HBG are assumed low for this timing.
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
tDRDHRDY
tDRDHRDY
Address Setup/CS Low Before RD Low1
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
0.5
0.5
6
0.5
0.5
0.5
0.5
6
0.5
0.5
ns
ns
ns
ns
ns
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
Data Valid Before REDY Disable from Low
1.5
1.5
ns
ns
ns
ns
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
11
9
11.5
9.5
45 + DT
1.5
45 + DT
1.5
tHDARWH
Write Cycle
Timing Requirements:
tSCSWRL
tHCSWRH
tSADWRH
tHADWRH
tWWRL
CS Low Setup Before WR Low
0.5
0.5
5.5
2.5
7
0.5
0.5
5.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
tWRWH
RD/WR High Width
6
6
tDWRHRDY
tSDATWH
tHDATWH
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
Data Hold After WR High
0.5
5.5
1.5
0.5
5.5
1.5
Switching Characteristics:
tDRDYWRL
tRDYPWR
tSRDYCK
REDY (O/D) or (A/D) Low Delay After WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
11
11.5
ns
ns
ns
15
15
1 + 7DT/16
9 + 7DT/16
0 + 7DT/16
8 + 7DT/16
NOT E
1Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. T his is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be
driven during asynchronous host accesses, see T able 8.2 of the ADSP-2106x SHARC User’s Manual.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19a. Synchronous REDY Tim ing
REV. A
–25–
ADI [ ADI ]
