AD14060/AD14060L
Thr ee-State Tim ing—Bus Master , Bus Slave,
,
T hese specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. T his timing is applicable to bus master tran-
sition cycles (BT C) and host transition cycles (HT C) as well as
the SBTS pin.
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Timing Requirements:
tST SCK
tHT SCK
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
12 + DT /2
12 + DT /2
ns
ns
5.5 + DT /2
5.5 + DT /2
Switching Characteristics:
tMIENA
tMIENS
Address/Select Enable After CLKIN
–1.5 – DT /8
–1.5 – DT /8
–1.5 – DT /8
–1.25 – DT /8
–1.5 – DT /8
–1.5 – DT /8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Strobes Enable After CLKIN1
HBG Enable After CLKIN
tMIENHG
tMIT RA
tMIT RS
Address/Select Disable After CLKIN
Strobes Disable After CLKIN1
HBG Disable After CLKIN
1 – DT /4
2.5 – DT /4
3 – DT /4
1 – DT /4
2.5 – DT /4
3 – DT /4
tMIT RHG
tDAT EN
tDAT T R
tACKEN
tACKT R
tADCEN
tADCT R
tMT RHBG
tMENHBG
Data Enable After CLKIN2
9 + 5DT /16
0 – DT /8
7.5 + DT /4
–1 – DT /8
–2 – DT /8
9 + 5DT /16
0 – DT /8
7.5 + DT /4
–1 – DT /8
–2 – DT /8
Data Disable After CLKIN2
8 – DT /8
7 – DT /8
9 – DT /4
8 – DT /8
7 – DT /8
9 – DT /4
ACK Enable After CLKIN2
ACK Disable After CLKIN2
ADRCLK Enable After CLKIN
ADRCLK Disable After CLKIN
Memory Interface Disable Before HBG Low3
Memory Interface Enable After HBG High3
–1 + DT /8
18.5 + DT
–1 + DT /8
18.5 + DT
NOT ES
1Strobes = RD, WR, SW, PAGE, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
tSTSCK
tHTSCK
SBTS
tMITRA, tMITRS, tMITRHG
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
ADRCLK
HBG
tADCEN
tADCTR
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 20. Three-State Tim ing
REV. A
–27–
ADI [ ADI ]
