ACT81460
Rev 1.0, 18-Dec-2018
internal power ok (POK) signal from one of the other
regulators, the internal VIN POK signal, or an external
signal applied to an input pin such as EXT_PG or GPIO.
This flexibility allows a wide range of sequencing
possibilities, including having some of the outputs be
sequenced with an external power supply or a control
signal from the host. As an example, if the LDO1 input
trigger is Buck1, LDO1 will not turn on until Buck1 is in
regulation. Input triggers are defined at the factory and
can only be changed with a custom CMI configuration.
The GPIOx outputs can be connected to an internal
power supply’s POK signal and used to trigger external
supplies in the overall sequencing scheme. The GPIOx
inputs can also be connected to an external power
supply’s power good output and used as an input trigger
for an ACT81460 supply.
or a GPIO. DVS allows systems to save power by
quickly adjusting the microprocessor performance level
when the workload changes. Note that DVS is not a
different operating state. The IC operates in the ACTIVE
state, but just regulates the outputs to a different voltage.
Each buck converter operates at its VOUT0 voltage in
normal operation and operates at its VOUT1 voltage
when the DVS input trigger is active. DVS can be
implemented three ways.
The first method is to individually put each buck
converter in DVS by manually writing a new voltage
regulation setpoint into its VOUT0 register.
DVS can also be implemented for both buck converters
at one time via a single GPIO input. The IC’s default CMI
determines the specific GPIO used for the DVS input.
Refer to the CMI Options section at the end of this
datasheet. This setting can be modified with a custom
CMI.
Turn-on Delay. The turn-on delay is the time between
an input trigger going active and the output starting to
turn on. Each output’s turn-on delay is configured via its
I2C bit ON DELAY. Turn-on delays can be changed after
the IC is powered on, but they are volatile and reset to
the factory defaults when power is recycled.
DVS can also be implemented for both buck converters
at one time via I2C. One of three I2C registers controls
each buck converters DVS function. Writing a 1 into the
appropriate register puts the buck converter into DVS.
The register choices are DVS_FROM_I2C_DB9,
DVS_FROM_I2C_DB10, and DVS_FROM_I2C_DB11.
Each buck’s DBSTBY register programs which register
enables its DVS function. The user can change the
default settings after power up.
Turn-off Delay. The turn-off delay is the time between
an input trigger going inactive and the output starting to
turn off. Each output’s turn-off delay is configured via its
I2C bit OFF DELAY. Turn-off delays can be changed
after the IC is powered on, but they are volatile and reset
to the factory defaults when power is recycled. Turn-off
delays are valid when entering SLEEP mode, DPSLP
mode, and when turning off the IC. Turn-off delays are
not implemented in fault conditions.
For CMI 101, Buck1 DVS is disabled by default. Buck2
is controlled by DVS_FROM_I2C_DB9. Writing a 1 into
this register puts Buck2 into DVS, but does not affect
Buck1. Note that each specific CMI allows DVS contro
by either a GPIO or I2C, but not both.
Output Voltage. The output voltage is each regulator’s
desired voltage. Each buck’s output voltage is
programmed via its I2C bits VSET0 and VSET1. The
output regulates to VSET0 in ACTIVE mode. They can
be programmed to regulate to VSET1 in DVS, SLEEP,
and DSPSLP modes. Each LDO has a single register,
VSET, to set its output voltage. Each output’s voltage
can be changed after the IC is powered on, but the new
setting is volatile and is reset to the factory defaults
when power is recycled. Output voltages can be
changed on the fly. If a large output voltage change is
required, it is best to make multiple smaller changes.
This prevents the IC from detecting an instantaneous
over or under voltage condition because the fault
thresholds are immediately changed, but the output
takes time to respond.
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage
condition does not exceed the current limit setting of the
regulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the
voltage step, slew rate, and load current conditions do
not result in an instantaneous loading that results in a
current limit condition.
Dynamic Voltage Scaling
On-the-fly dynamic voltage scaling (DVS) for the two
buck converters is available via either the I2C interface
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