ACT81460
Rev 1.0, 18-Dec-2018
The I2C bit DPSLP MODE is set at factory and cannot
be changed by the user. It controls the logical combina-
tion of the GPIO input and the DPSLP register bit to en-
ter DPSLP state. When DPSLP MODE is factory con-
figured to 1, the logical combination is an “OR” function
and when DPSLP is factory configured to a 0, the logical
combination is an “AND” function.
The IC exits the DPSLP state when the conditions to
enter DPSLP state are no longer present. The IC also
exits the DPSLP state when nPBIN is pulled low
for >32ms. This also clears the DPSLP register bits.
When the IC exits the DPSLP state, it goes through a
full power ON sequence before entering the POWER
ON state.
Table 1a. SLEEP Mode Truth Table (SLEEP MODE bit
is configured to 0)
If no GPIOs are configured as a control input to enter
and exit DPSLP state then only the DPSLP register bit
controls the entry and exit of the DPSLP state.
Table 2a and 2b show the conditions to enter DPSLP
state.
Table 1b. SLEEP Mode Truth Table (SLEEP MODE bit
is configured to 1)
DPSLP State
Table 2a. DPSLP Mode Truth Table (DPSLP MODE
factory bit is configured to 0)
The DPSLP state is another low power operating mode
for the operating system. It is intended to be used in a
lower power configuration than the SLEEP mode. It is
similar to the SLEEP state, but DPSLP uses slightly dif-
ferent configurations to enter and exit this mode. Each
output can only be programmed to be on or off in the
DPSLP state. The DPSLP state does not allow the au-
tomatic use of the VSET1 registers. This programming
can be different and independent from the SLEEP state.
The outputs follow their programmed sequencing delay
times when turning on or off as they enter or exit the
DPSLP state.
The IC enters DPSLP state via I2C register bits DPSLP,
DPSLP EN, and DPSLP MODE, plus a GPIO input pin.
The IC’s specific CMI determines the specific combina-
tion of these three inputs to enter DPSLP state.
ACT81460’s I2C stays enabled in DPSLP state.
Table 2b. DPSLP Mode Truth Table (DPSLP MODE
factory bit is configured to 1)
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