ACT81460
Rev 1.0, 18-Dec-2018
If a DC/DC's nFLTMSK bit is set to 1, the ACT81460
interrupts the processor if the DC/DC's output voltage
falls below the Power-OK (POK) threshold. In this case,
nIRQ asserts low and remains asserted until either the
regulator is turned off or the output goes back into reg-
ulation, and the POK bit has been read via I2C. The POK
interrupt is cleared when the register is read and the
fault is no longer present.
Active Semi recommends that the buck converter’s out-
put voltage be kept within +/- 20% of the default output
voltage to maintain accuracy. Voltage changes larger
than +/- 20% may require different factory trim settings
(new CMI) to maintain accuracy.
Dynamic Voltage Scaling
Each buck converter supports Dynamic Voltage Scaling
(DVS). In normal operation, each output regulates to the
voltage programmed by its VSET0 register. During DVS,
each output can be programmed to regulate to its
VSET0 or VSET1 voltage.
Minimum On-Time
ACT81460 does not have minimum on-time limitations
that prevent the use of any desired switching frequency.
Overcurrent and Short Circuit Protection
When DVS is enabled via I2C, the IC’s digital core steps
the output setting through each voltage step between
the initial and final settings. This ensures a constant and
controlled slew rate. During a high to low voltage transi-
tion, the regulator switches in an internal 40Ω resistor to
ensure the output voltage maintains a constant slew
rate under light load conditions.
Each buck converter provides overcurrent and short cir-
cuit protection. Overcurrent protection is achieved with
cycle-by-cycle current limiting. The peak current thresh-
old is set by the ILIM_SET I2C bits.
If the peak current reaches the programmed threshold,
the IC turns off the power FET for that switching cycle.
If the load current continues to increase, this condition
results in shutdown due to an UV condition from the
shortened switching cycle.
When switching between VSET0 and VSET1 in DVS
mode, the digital core steps the output voltage between
the two values one register step at a time. During this
transition, the regulator’s OV and UV faults are ignored
to prevent false fault conditions. Also for DVS, it is rec-
ommended to keep the range within +-20% of the nom-
inal CMI set point. In some cases, greater than 20% de-
viation would be allowed.
If the short circuit or overload condition occurs quickly,
the cycle-by-cycle current can exceed the programmed
threshold. When it reaches 125% of the programmed
current for two consecutive switching cycles, the IC is-
sues an overcurrent warning and asserts nIRQ low.
When it reaches 125% of the programmed current for
eight consecutive switching cycles, the buck converter
shuts down.
Note that if the user changes the VSETx register while
the buck converter is regulating to that register setting,
the IC does not mask out the OV and UV faults. Either
make small voltage steps or mask OV and UV fault reg-
isters to prevent a fault condition.
Compensation
The BUCK regulators utilize a proprietary internal com-
pensation scheme to simultaneously simplify external
component selection and optimize transient perfor-
mance over their full operating range. No compensation
design is required; simply follow a few simple guide
lines described below when choosing external compo-
nents.
Enable / Disable Control
During normal operation, each buck may be enabled or
disabled via the I2C interface by writing to that regula-
tor's ON bit. Note that disabling a regulator that is used
as an input trigger to another regulator may or may not
disable the other regulators following it, depending on
the specific CMI settings. Each buck converter has a
load discharge function designed to quickly pull the out-
put voltage to ground when the converter is disabled.
The circuit connects an internal resistor (41ohm) from
the output to PGND when the converter is disabled.
Input Capacitor Selection
Each buck converter has a dedicated input pin and
power ground pin. Each buck converter must have a
dedicated input capacitor that is optimally placed to min-
imize the power routing loops for each buck converter.
Note that even though each buck converter has sepa-
rate inputs, all buck converter inputs must be connected
to the same voltage potential.
POK and Output Fault Interrupt
Each DC/DC features a Power-OK (POK) status bit that
can be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the power-
OK threshold, typically 8.0% below the programmed
regulation voltage, that regulator’s POK bit will be 0.
Each regulator requires a high quality, low-ESR, ce-
ramic input capacitor. 1uF capacitors are typically suit-
able, but this value can be increased without limit.
Smaller capacitor values can be used with lighter output
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