ACT81460
Rev 1.0, 18-Dec-2018
VIO_IN
GPIOx Configurability
VIO_IN is the input bias supply for the IC. Apply an input
voltage between 1.2V and the VSYS voltage. Bypass to
AGND with a high quality, 1uF ceramic capacitor.
The ACT81460 has four GPIO pins. These GPIOs allow
a variety of functions to be implemented. They can be
used as inputs, push-pull outputs, open drain outputs,
LED drivers, or as analog input/output. These options
allow implementation of a variety of system functions
and also allow flexibility of functions tied to each pin.
Some examples of system functions that can be imple-
mented are nRESET, Power Good (PG) output, inter-
rupt request or interrupt pin (nIRQ), digital output from
power okay (POK) signal from individual regulators, dig-
ital input to control power sequencing or regulator
ON/Off, control input used to enter or exit sleep (SLEEP)
and deep sleep (DPSLP) modes, input/output lines to
sequence external regulators as part of the power se-
quence, to control Dynamic Voltage Scaling (DVS) in
BUCK regulators or even as LED drivers.
FBx
These are the regulation pins for the converters. Kelvin
connect these pins to their respective output capacitors.
PGNDx
The PGNDx pins are dedicated power grounds for each
switching converter. The input caps should be directly
connected to the PGNDx pins.
SWBST
SWBST is the boost converter switch node. Connect the
boost inductor directly to this pin.
SCL, SDA
The GPIOs are internally powered by the VIN_IO pin.
The user should ensure that the resulting input and out-
put voltages are compatible with their system level in-
puts and outputs.
SCL and SDA are the I2C clock and data pins to the IC
They have standard I2C functionality. They are open-
drain outputs and each require a pull-up resistor. The
pull-up resistor is typically tied to the system’s uP IO
pins. The pullup voltage can range from 1.8V to 5.0V.
SCL and SDA are open drain and are 5V compliant.
GPIO1 (pin D3). GPIO1 can be programmed for any of
the above functions except the LED drivers. It can be
programmed as an input or an open drain or push-pull
output.
AGND
GPIO2 (pin C3). GPIO2 is the same as GPIO1
The AGND pins are the IC’s analog ground. This is a
“quiet” ground pin that is separate and isolated from the
high power, high current carrying PGND ground plane.
Connect the non-power components to AGND. AGND
must be Kelvin connected to the PGND pin in a single
location.
GPIO3 (pin E4). GPIO3 can be programmed for all the
above functions including the LED drivers. It can be pro-
grammed as an input or an open drain output.
GPIO4 (pin E5). GPIO4 is the same as GPIO3
The GPIOs are 5.5V tolerant meaning they can go to
5.5V even if VIN_IO is less than 5.5V.
nPBIN
nPBIN is the push button input pin and provides multiple
system level functions based on its impedance to
ground and “press” time. See the Pushbutton Function-
ality section of the datasheet for more details.
When GPIO1 and GPIO2 are configured as LED drivers,
they sink a constant current. The constant current is de-
fined by the I2C bits ILED_SET per Table 3.
nIRQ
nIRQ informs the host of any fault conditions. In general,
any IC function with a status bit asserts nIRQ pin low if
the status changes. The status changes can be masked
by setting their corresponding register bits. If nIRQ is
asserted low, the fault must be read before the IC deas-
serts nIRQ. If the fault remains after reading the status
bits, nIRQ remains asserted. Refer to the nIRQ Inter-
rupt Pin (nIRQ) section for more details.
ISET [5:3]
0
0
1
2
3
4
5
6
7
1
8
000
001
010
011
100
101
110
111
10
12
14
16
18
20
22
nIRQ is an open-drain output and should be pulled up
to an appropriate supply voltage with a 10kΩ or greater
pull-up resistor. nIRQ is 5V compliant.
Table 3. Constant Current vs ISET Register
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