ACT81460
Rev 1.0, 18-Dec-2018
nPBIN is released high, the IC follows normal pro-
grammed functionality to leave the POWER OFF state.
If nPBIN is pulled low for >8s but <12s, the IC follows
the Power Cycle1 sequencing described above.
masked to prevent false overcurrent conditions. The
current limit is unmasked after the softstart time is com-
plete and it then ready to detect over current faults.
Smart Switch – OVP
Soft Reset – This sequence pulls nRESET low to reset
the system processor, but all ACT81460 outputs stay
turned on. To initiate Soft Reset, pull nPBIN to ground
through a 1kΩ resistor for 2s to 4s. nRESET asserts low
after 2s. When nPBIN transitions back high, the IC de-
asserts the nRESET pin high. The output voltages do
not power cycle during a Soft Reset.
The Smart Switch also provides over voltage protection.
When VIN goes above 5.8V, the IC generates a fault
condition. The typical deglitch time for detecting an OV
condition is 200us. The Smart Switch is latched open
until the over voltage condition is removed. After the
fault clears, the Smart Switch restarts. The typical retry
time after the OV or any other fault condition clears is
20ms.
Power Cycle2 (Hard Reset) – This sequence momen-
tarily turns all outputs off and automatically restarts
them. Initiate Power Cycle2 by momentarily pulling
nPBIN to ground through a 1kΩ resistor for >4s. When
nPBIN transitions back high, the IC transitions from its
current operating state to the POWER OFF state for
0.5s. It then transitions to the START POWER SE-
QUENCE START state for 0.5s before going to the
POWER IN state. Unlike Power Cycle1, the Power Cy-
cle2 sequence does not require any I2C register settings.
Watchdog Supervision
The ACT81460 features a watchdog supervisory func-
tion. This resets the system in the case where the host
microprocessor get locked up or becomes unrespon-
sive. Watchdog is disabled by default. Writing a 1 into
I2C bits WDSREN or WDPCEN enables the watch dog
functionality. Once enabled, the watchdog timer is reset
whenever there is I2C activity. If there is no I2C commu-
nication for longer than 8s, the IC performs either a soft-
reset if the WDSREN bit = 1 or a power cycle if the
WDPCEN bit = 1. If both bits = 1, the IC performs Power
Cycle
Software-Initiated Power Cycle
ACT81460 supports a software-initiated power cycle.
This is initiated by setting I2C bit MR to 1. The IC then
waits 8ms and initiates a power cycle to restart the sys-
tem. MR is automatically reset to 0 after the power cycle.
Fault Protection
The ACT81460 contains several levels of fault protec-
tion, including the following:
Smart Switch – Softstart
The ACT81460 is specifically designed to system level
handle hot plug events. It does this with a combination
of the 20V input blocking capability and inrush current
control at startup. When power is applied to the VIN pin,
the IC monitors the VIN voltage after it is greater than
approximately 1.5V. VIN is then monitored for under
voltage (UV), ~4.0V, and over voltage (OV) conditions,
~5.8V. When VIN is in the valid range, the Smart Switch
connects the VIN to VSYS. The Smart Switch slowly
ramps up the VSYS by limiting the inrush current. The
Smart Switch current limit is programmed by the I2C bit
IN_ILIM_SETTING between 0.5A and 2A. The inrush
controller thus limits inrush current while also adding
monitoring and health check functions such as UV, OV
and Over Current Protection (OCP) on the VIN input.
Output Overvoltage
Output Undervoltage
Output Current Limit and short circuit
Thermal Shutdown
There are two types of I2C register bits associated with
each fault condition: fault bits and mask bits. The mask
bits either block or allow the fault to affect the fault bit.
Each potential fault condition can be masked via I2C if
desired. Any unmasked fault condition results in the
fault bit going high, which asserts the nIRQ pin. The
nIRQ pin only de-asserts after the fault condition is no
longer present and the corresponding fault bit is read
via I2C. If a fault is masked, the fault bit shows the real-
time fault status, but the fault does not assert nIRQ. Re-
fer to Active-Semi Application Note describing the Reg-
ister Map for full details on I2C functionality and pro-
gramming ranges.
Smart Switch – Current Limit
The Smart Switch also provides input current limit circuit
in normal operation. The Smart Switch current limit is
programmed by the I2C bit IN_ILIM_SETTING between
0.5A and 2A. In the event of an overcurrent, the Smart
Switch opens and disconnects VIN from VSYS. After a
20ms re-try timer expires, the Smart Switch restarts.
During the softstart time, the Smart Switch limits the in-
rush current. During this time the current limit signal is
nIRQ (Interrupt)
nIRQ is an open-drain output that asserts low any time
an interrupt is generated. This function can be
configured on any of the GPIOs even though GPIO1 is
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