PLUS
ProASIC
Flash Family FPGAs
PLL Electrical Specifications
Parameter
Value
Notes
Frequency Ranges
Reference Frequency fIN (min.)
Reference Frequency fIN (max.)
OSC Frequency fVCO (min.)
OSC Frequency fVCO (max.)
Clock Conditioning Circuitry fOUT (min.)
Clock Conditioning Circuitry fOUT (max.)
Long Term Jitter Peak-to-Peak Max.*
Temperature
1.5 MHz
180 MHz
24 MHz
180 MHz
6 MHz
Clock conditioning circuitry (min.) lowest input frequency
Clockconditioning circuitry (max.) highest input frequency
Lowest output frequency voltage controlled oscillator
Highest output frequencyvoltage controlledoscillator
Lowest output frequency clock conditioning circuitry
Highest output frequency clock conditioning circuitry
180 MHz
Frequency MHz
f
VCO<10
10<fVCO<60 fVCO>60
25°C (or higher)
1ꢀ
2ꢀ
1ꢀ
Jitter(ps) = Jitter(ꢀ)*period
For example:
Jitter in picoseconds at 100 MHz
= 0.01 * (1/100E6) = 100 ps
0°C
1.5ꢀ
2.5ꢀ
2.5ꢀ
2.5ꢀ
3.5ꢀ
3.5ꢀ
1ꢀ
1ꢀ
1ꢀ
–40°C
–55°C
Acquisition Time from Cold Start
Acquisition Time (max.)
Acquisition Time (max.)
Power Consumption
Analog Supply Power (max.*)
Digital Supply Current (max.)
Duty Cycle
30 µs
80 µs
fVCO ≤ 40 MHz
fVCO > 40 MHz
6.9 mW per PLL
7 µW/MHz
50ꢀ 0.5ꢀ
5ꢀ input period (max. 5 ns)
Maximum jitter allowable on an input clock to
acquire and maintain lock.
Input Jitter Tolerance
Note: *High clock frequencies (>60 MHz) under typical setup conditions
v5.2
1-21
ACTEL [ Actel Corporation ]
