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A32100DX-CQ84B 参数 Datasheet PDF下载

A32100DX-CQ84B图片预览
型号: A32100DX-CQ84B
PDF下载: 下载PDF文件 查看货源
内容描述: HiRel它的FPGA [HiRel FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 98 页 / 2009 K
品牌: ACTEL [ Actel Corporation ]
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A1240A Timing Characteristics (continued)  
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)  
‘–1’ Speed  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
Input Module Propagation Delays  
tINYH  
tINYL  
tINGH  
tINGL  
Pad to Y High  
Pad to Y Low  
G to Y High  
G to Y Low  
4.0  
3.6  
6.9  
6.6  
4.7  
4.3  
8.1  
7.7  
ns  
ns  
ns  
ns  
Input Module Predicted Routing Delays1  
tIRD1  
tIRD2  
tIRD3  
tIRD4  
tIRD8  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
5.8  
6.7  
6.9  
7.8  
ns  
ns  
ns  
ns  
ns  
7.5  
8.8  
8.2  
9.7  
10.9  
12.9  
Global Clock Network  
tCKH Input Low to High  
FO = 32  
FO = 256  
13.3  
16.3  
15.7  
19.2  
ns  
ns  
tCKL  
Input High to Low  
FO = 32  
FO = 256  
13.3  
16.5  
15.7  
19.5  
tPWH  
tPWL  
tCKSW  
tSUEXT  
tHEXT  
tP  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Maximum Skew  
FO = 32  
FO = 256  
5.7  
6.0  
6.7  
7.1  
ns  
FO = 32  
FO = 256  
5.7  
6.0  
6.7  
7.1  
ns  
FO = 32  
FO = 256  
0.6  
3.1  
0.6  
3.1  
ns  
Input Latch External Setup  
Input Latch External Hold  
Minimum Period  
FO = 32  
FO = 256  
0.0  
0.0  
0.0  
0.0  
ns  
FO = 32  
FO = 256  
8.6  
13.8  
8.6  
13.8  
ns  
FO = 32  
FO = 256  
11.5  
12.2  
13.5  
14.3  
ns  
fMAX  
Note:  
Maximum Frequency  
FO = 32  
FO = 256  
87  
82  
74  
70  
MHz  
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is  
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce  
delays by 0 to 4 ns.  
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