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A32100DX-CQ84B 参数 Datasheet PDF下载

A32100DX-CQ84B图片预览
型号: A32100DX-CQ84B
PDF下载: 下载PDF文件 查看货源
内容描述: HiRel它的FPGA [HiRel FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 98 页 / 2009 K
品牌: ACTEL [ Actel Corporation ]
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HiRel FPGAs  
A1240A Timing Characteristics  
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)  
‘–1’ Speed  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
Logic Module Propagation Delays1  
tPD1  
tCO  
tGO  
tRS  
Single Module  
5.2  
5.2  
5.2  
5.2  
6.1  
ns  
ns  
ns  
ns  
Sequential Clk to Q  
Latch G to Q  
6.1  
6.1  
6.1  
Flip-Flop (Latch) Reset to Q  
Logic Module Predicted Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
1.9  
2.4  
3.1  
4.3  
6.6  
2.2  
2.8  
3.7  
5.0  
7.7  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing3, 4  
tSUD  
Flip-Flop (Latch) Data Input Setup  
0.5  
0.0  
1.3  
0.0  
0.5  
0.0  
1.3  
0.0  
ns  
ns  
ns  
ns  
tHD  
Flip-Flop (Latch) Data Input Hold  
Flip-Flop (Latch) Enable Setup  
Flip-Flop (Latch) Enable Hold  
tSUENA  
tHENA  
tWCLKA  
Flip-Flop (Latch) Clock Active Pulse  
Width  
7.4  
8.1  
ns  
tWASYN  
Flip-Flop (Latch) Asynchronous Pulse  
Width  
7.4  
14.8  
2.5  
8.1  
18.6  
2.5  
ns  
ns  
tA  
Flip-Flop Clock Input Period  
Input Buffer Latch Hold  
tINH  
ns  
tINSU  
tOUTH  
tOUTSU  
fMAX  
Notes:  
Input Buffer Latch Setup  
Output Buffer Latch Hold  
Output Buffer Latch Setup  
Flip-Flop (Latch) Clock Frequency  
–3.5  
0.0  
–3.5  
0.0  
ns  
ns  
0.5  
0.5  
ns  
63  
54  
MHz  
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based  
on actual routing delay measurements performed on the device prior to shipment.  
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from  
the DirectTime Analyzer utility.  
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold  
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input  
subtracts (adds) to the internal setup (hold) time.  
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