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A32100DX-CQ84B 参数 Datasheet PDF下载

A32100DX-CQ84B图片预览
型号: A32100DX-CQ84B
PDF下载: 下载PDF文件 查看货源
内容描述: HiRel它的FPGA [HiRel FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 98 页 / 2009 K
品牌: ACTEL [ Actel Corporation ]
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ACT 1 Timing Characteristics (continued)  
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)  
‘–1’ Speed  
‘Std’ Speed  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Units  
Global Clock Network  
tCKH  
tCKL  
tPWH  
tPWL  
tCKSW  
tP  
Input Low to High  
FO = 16  
FO = 128  
7.8  
8.9  
9.2  
10.5  
ns  
ns  
Input High to Low  
FO = 16  
FO = 128  
10.3  
11.2  
12.1  
13.2  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Maximum Skew  
FO = 16  
FO = 128  
10.4  
10.9  
12.2  
12.9  
ns  
FO = 16  
FO = 128  
10.4  
10.9  
12.2  
12.9  
ns  
FO = 16  
FO = 128  
1.9  
2.9  
2.2  
3.4  
ns  
Minimum Period  
FO = 16  
FO = 128  
21.7  
23.2  
25.6  
27.3  
ns  
fMAX  
Maximum Frequency  
FO = 16  
FO = 128  
46  
44  
40  
37  
MHz  
TTL Output Module Timing1  
tDLH  
Data to Pad High  
12.1  
13.8  
12.0  
14.6  
16.0  
14.5  
0.09  
0.12  
14.2  
16.3  
14.1  
17.1  
18.8  
17.0  
0.11  
0.15  
ns  
ns  
tDHL  
Data to Pad Low  
tENZH  
tENZL  
tENHZ  
tENLZ  
dTLH  
dTHL  
Enable Pad Z to High  
Enable Pad Z to Low  
Enable Pad High to Z  
Enable Pad Low to Z  
Delta Low to High  
Delta High to Low  
ns  
ns  
ns  
ns  
ns/pF  
ns/pF  
CMOS Output Module Timing1  
tDLH  
Data to Pad High  
15.1  
11.5  
12.0  
14.6  
16.0  
14.5  
0.16  
0.09  
17.7  
13.6  
14.1  
17.1  
18.8  
17.0  
0.18  
0.11  
ns  
ns  
tDHL  
Data to Pad Low  
tENZH  
tENZL  
tENHZ  
tENLZ  
dTLH  
dTHL  
Notes:  
Enable Pad Z to High  
Enable Pad Z to Low  
Enable Pad High to Z  
Enable Pad Low to Z  
Delta Low to High  
Delta High to Low  
ns  
ns  
ns  
ns  
ns/pF  
ns/pF  
1. Delays based on 50 pF loading.  
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at  
http://www.actel.com/appnotes.  
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