HiRel FPGAs
ACT 1 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
4.7
10.8
4.7
5.5
ns
ns
ns
ns
ns
Dual Module Macros
Sequential Clk to Q
Latch G to Q
12.7
5.5
4.7
5.5
Flip-Flop (Latch) Reset to Q
4.7
5.5
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.5
2.3
1.7
2.7
ns
ns
ns
ns
ns
3.4
4.0
5.0
5.9
10.6
12.5
Logic Module Sequential Timing 2
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
8.8
0.0
8.8
0.0
10.4
0.0
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
10.4
0.0
Flip-Flop (Latch) Clock Active Pulse
Width
10.9
12.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
10.9
23.2
12.9
27.3
ns
ns
tA
Flip-Flop Clock Input Period
fMAX
Flip-Flop (Latch) Clock
Frequency
44
37
MHz
Input Module Propagation Delays
tINYH
tINYL
Pad to Y High
4.9
4.9
5.8
5.8
ns
ns
Pad to Y Low
Input Module Predicted Routing Delays1, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.5
2.3
1.7
2.7
ns
ns
ns
ns
ns
3.4
4.0
5.0
5.9
10.6
12.5
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
25
ACTEL [ Actel Corporation ]
