欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-0421901QYC 参数 Datasheet PDF下载

5962-0421901QYC图片预览
型号: 5962-0421901QYC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, 4224-Cell, CMOS, CQFP208, CERAMIC, QFP-208]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号5962-0421901QYC的Datasheet PDF文件第30页浏览型号5962-0421901QYC的Datasheet PDF文件第31页浏览型号5962-0421901QYC的Datasheet PDF文件第32页浏览型号5962-0421901QYC的Datasheet PDF文件第33页浏览型号5962-0421901QYC的Datasheet PDF文件第35页浏览型号5962-0421901QYC的Datasheet PDF文件第36页浏览型号5962-0421901QYC的Datasheet PDF文件第37页浏览型号5962-0421901QYC的Datasheet PDF文件第38页  
MIL-PRF-38535K  
TABLE IA. Screening procedure for hermetic classes Q, V and non-hermetic class Y microcircuits - Continued.  
1/ Testing per manufacturer’s QM plan. See paragraph H.3.2.1.4 of MIL-PRF-38535 or TM 5007 of MIL-STD-883.  
2/ For flip chip packages Nondestructive bond pull (NDBP) test is not required.  
3/ Unless otherwise specified, at the manufacturer's option for test samples selection of group B, bond strength test (method 5005) may  
be randomly selected prior to or following internal visual (method 5004), prior to sealing provided all other specification requirements  
are satisfied (e.g., bond strength requirements shall apply to each inspection lot, bond failures shall be counted even if the bond  
would have failed internal visual exam), and unsealed microcircuits awaiting further processing shall be stored in a dry, inert,  
controller environment until sealed. Test method 2010 applies in full except when method 5004, alternate 1 or alternate 2 (appendix  
A) is in effect (see 3.3 method 5004 of MIL-STD-883). For gallium arsenide (GaAs) devices only, TM 5013 of MIL-STD-883 should be  
used. For flip chip devices, both internal visual and C-SAM inspection (such as prior to bump attach to die and after bump attach to  
substrate and underfill cured etc.) shall be performed in accordance with TM 2010 and TM 2030.  
4/ For devices with solder terminations, Temperature cycling test may be performed without balls and columns upon approval of PIDTP  
and QM plan.  
5/ All microcircuits shall be subjected to constant acceleration. For microcircuits which are contained in packages that have an  
inner seal or cavity perimeter of 2 inches or more in total length or have a package mass of 5 grams or more may be tested by  
replacing test condition E with condition D or with test conditions as specified in the applicable device specification. Unless  
otherwise specified in the acquisition document, the stress level for large, monolithic microcircuit packages shall not be reduced  
below test condition D. If the stress level specified is below condition D, the manufacturer must have data to justify this reduction  
and this deviation shall be specified in the QM plan, and data available for review by the preparing or acquiring activity. The  
minimum stress level allowed in this case is condition A. For flip chip devices, Constant acceleration test is not required.  
6/ At the manufacturer's option, external visual inspection for catastrophic failures may be conducted after each of the  
thermal/mechanical screens, after the sequence or after seal test. Catastrophic failures are defined as missing leads, broken  
packages, or lids off.  
7/ See paragraph A.4.6.3 of appendix A and paragraph B.4.1 of appendix B of MIL-PRF-38535. The PIND test may be performed  
in any sequence after temperature cycling test and prior to post burn-in (interim) electrical parameters test.  
8/ For device without a cavity or for flip chip devices with underfill, PIND test is not applicable.  
9/ Class V or class Y (class level S) devices shall be serialized prior to the first recorded electrical measurement in screening. Class  
Q (class level B) microcircuits shall be serialized if delta calculations or matching characteristics are a requirement of the device  
specification. Each microcircuit shall be assigned a unique serial number in order to trace the data back to an individual device  
within the inspection lot which shall, in turn, be traceable to the wafer lot from which the device originated.  
10/ Interim (pre and post burn-in) electrical testing shall be performed when specified, to remove defective devices prior to further  
testing or to provide a basis for application of percent defective allowable (PDA) criteria when PDA is specified (Ref. test step 14:  
PDA calculation, and footnote 17 herein). If no device specification or drawing exists, subgroups tested shall at least meet those  
of the most similar device specification or standard microcircuit drawing (SMD). This test need not include all specified device  
parameters, but shall include those measurements that are most sensitive to the time and temperature effects of burn-in and the  
most effective in removing electrically defective devices.  
11/ When specified in the applicable device specification, 100 percent of the devices shall be tested and the results recorded for  
those parameters requiring delta calculations.  
12/ For class V and class Y (class level S) microcircuit devices, delta measurements shall be performed. The specific delta  
parameters shall be as defined in the applicable device specification. Pre burn-in and post burn-in interim electrical parameters  
shall be read and recorded when delta measurements have been specified as part of post burn-in electrical measurements, 100  
percent of the devices shall be tested and the results shall be recorded for those parameters requiring delta calculations.  
20  
 
 复制成功!