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5962-0421901QUA 参数 Datasheet PDF下载

5962-0421901QUA图片预览
型号: 5962-0421901QUA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 250000 Gates, CMOS, CPGA624, CERAMIC, CGA-624]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX H  
d. Testability and fault coverage verification. The manufacturer should demonstrate a design style and a design-for-test  
(DFT) methodology that, in conjunction with demonstrated CAD for test tools, can provide 99 percent or greater fault  
coverage on a design of reasonable complexity. The manufacturer should also address their approach for a testability  
bus to groups such as the Joint Test Action Group (JTAG). The manufacturer should demonstrate the fault coverage  
measurement (fault simulation, test algorithm analysis, etc.) capability that is used to provide fault coverage statistics  
of the design using the demonstrated design style, DFT method and CAD for test tools. Measurement of fault  
coverage should be in accordance with the procedures defined in TM 5012 of MIL-STD-883. For non-digital  
microcircuits, the fault coverage requirement may not be applicable, but should be supplemented as measures of  
analog fault coverage become better defined. For microcircuits with both analog and digital functions, this requirement  
fully applies to the digital portions of the microcircuits.  
H.3.2.1.1.2 Design checklist (Class level S) . The following items shall be used as minimum requirements, as applicable for  
the technology, for the manufacturer and QA in evaluating the new technology for class level S product:  
a. Design environment/infrastructure.  
(1) Project schedule.  
(2) Resource management (e.g., designers, hardware, software development).  
(3) Historical factors (e.g., any pertinent information based on previous designs, design rules, lessons learned, etc.).  
(4) Tools and design flow.  
(5) ASIC cell library and design kit.  
(6) Intellectual property (IP, e.g., any pertinent information such as use of 3rd party licensed IP, IP developed by  
another entity or manufacturer, etc.).  
(7) Models (for those developing their own cell libraries, and ASIC design kits), for analog/signal  
integrity simulations, and power calculations.  
b. Detailed design hardware description language (HDL) coding (first phase of design).  
(1) Specification development guidelines (e.g., what design information must be included in the specification).  
(2) HDL coding guidelines.  
(3) Design for test (DFT) insertion and fault testing.  
(4) Built-in self test (BIST).  
c. Validation/verification of modules and top level design.  
(1) Fault coverage percentage.  
(2) Emulation/prototyping.  
(3) Radiation effects mitigation.  
d. Synthesis, static timing.  
(1) Foundry synthesis guidelines – Handoff to design team  
(2) Formulation of constraints from specification/requirements.  
(3) Synthesis and statically timed net list – Correlated with original HDL.  
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