W89C840F
The data flow of the packet transmission is shown as the following diagram
PCI
data
to
data
buffer 1
data
MAC
long word
aligning buffer
2 Kbytes
FIFO
data
buffer 2
data
buffer 3
control
Tx
descriptor 1
controls
from/to
MAC
Tx
PCI
master
transmission
DMA
state machine
descriptor 2
Tx
descriptor 3
data
buffer n
Tx
PCI slave
descriptor n
The data to be transmitted is stored in the transmit data buffer in the host memory. The t r ansmi t
DMA state machine will fetch the data in the host memory into the transmit FIFO, when the
t r ansmi ssi on DMA i s st ar t ed. All of the data fetched from the data buffer will be long word aligned
before being queued into the transmission FIFO. The driver program can inform the transmit DMA the
location of the data to be transmitted in the host memory and then the transmit DMA will fetch the data
from that location directly. Because the address of the data may not be l ong wor d al i gned, so the
transmit DMA need to align the data for passing the data to the MAC in a long word aligned format. The
aligned long word data, and then, is queued into the transmit FIFO. The transmission DMA will not
request the MAC to fetch the data in the FIFO for transmitting until the byte count of the data in the FIFO
is reach the threshold defined by C18/CNCR bit 14~20.
The t r ansmi t DMA is implemented a pre-fetch function for speeding the transmit performance.
With this implementation, the transmit DMA will pre-fetch the next packet data in the host memory after
the current packet data is moved into the transmit FIFO completely. Before starting to fetch the next packet
data, the transmit DMA will assert an interrupt if the transmit early interrupt is enabled. If there is no more
packet to be transmitted, the transmit DMA will report a buffer unavailable status and assert an interrupt if
the transmit buffer unavailable interrupt is enabled. After all of the current packet data in the transmit FIFO
are transferred out by the MAC block, the transmit DMA will try to fetch the next packet data again
automatically if the transmit DMA is not fetching the data from the host memory. A packet transmit
interrupt will be asserted when the current packet is transmitted if the packet transmitted interrupt is
enabled.
The transmit DMA will write back the current packet transmit status into the first descriptor of the
current transmit packet when the packet is successfully transmitted or is aborted due to excessive collision.
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ETC [ ETC ]
