W89C840F
For consecutively transmitting multiple packets, the software driver can previously program all the
packet data in the host memory and then release the access right to the W89C840F. Once the transmit
DMA is turned on, the DMA will transmit all of the packet out automatically. The inter-frame gap between
these packets will be specified by the MAC block for complying with the IEEE802.3u specification.
For concurrently processing the packet s t r ansmi t t i ng, t he t r ansmi t DMA asserts the transmit
early interrupt to trigger the software driver to set up the next t r ansmi t t i ng packet dat a earlier. The
data transmission rate on the MII bus can be ei t her 10 Mbps or 100 Mbps t hat is quite lower than the
rate on PCI bus. Mostly, the packet data is not yet completely transmitted onto the MII bus even though the
packet data with only a few bytes have been all moved into the transmit FIFO, the transmission DMA still
does not issue an interrupt to host. This will drop the transmit performance if the software driver waits for
the current packet being transmitted onto the MII completely and then set up the next packet data. The
transmit early interrupt can avoid the time consumption when waiting for the transmit completion of the
current packet occurs.
Media Access Control function(MAC)
The function of W89C840F MAC fully meets the requirements, defined by the IEEE802.3u
specification. The following paragraphs will describe the frame structure and the operation of the
transmission and receive.
The transmission data frame sent from the transmit DMA will be encapsulated by the MAC
before transmitting onto the MII bus. The sent data will be assembled with the preamble, the start frame
delimiter(SFD), the frame check sequence and the padding for enforcing those less than 64 bytes to meet
the minimum size frame and CRC sequence.
The out going frame format will be as following
10101010- - - - 101010101010111 d0 d1 d2 -- dn padding CRC31 CRC30 --- CRC0
As mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern
10101010 and the SFD is a one byte 10101011 data. The padding data will be all 0 value if the sent
data frame is less than 64 bytes. The padding disable function specified in the bit23 of the transmit
descriptor T01 is used to control if the MAC needs to pad data at the end of frame data or not when the
transmitted data frame is less than 64 bytes. The padding data will not be appended if the padding
disable bit is set to high. The bits CRC0 ... CRC31 are the 32 bits cyclic redundancy check(CRC)
sequence. The CRC encoding is defined by the following polynomial specified by the IEEE802.3.
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1
These 32 bits CRC appending function will be disabled if the Inhibit CRC of the transmission
descriptor T01 is set to high.
Publication Release Date:April 1997
- 17 -
Revision A1
ETC [ ETC ]
