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W89C840F 参数 Datasheet PDF下载

W89C840F图片预览
型号: W89C840F
PDF下载: 下载PDF文件 查看货源
内容描述: 局域网节点控制器\n [LAN NODE CONTROLLER ]
分类和应用: 控制器局域网
文件页数/大小: 72 页 / 708 K
品牌: ETC [ ETC ]
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W89C840F  
The MAC also performs many other transmission functions specified by the IEEE802.3,  
including the inter-frame spacing function, collision detection, collision enforcement, collision backoff  
and re-transmission. The collision backoff timer is a function of the integer slot time, 512 bit times. The  
number of slot times to delay between the current transmission attempt to the next attempt is determined  
by a uniformly distributed random integer algorithm specified by the IEEE802.3. The integer, r, is  
specified as the following  
0 £ r £ 2k  
where k = min.(n, 10)  
The MAC performs the receive functions specified by the IEEE802.3 including the address  
recognition function, the frame check sequence validation, the frame disassembly, framing and collision  
filtering.  
The W89C840F categorizes the input stream from media into three types of frame. These three  
types are the packet with unicast destination address, the multicast destination address and the broadcast  
destination address. A unicast address is defined as a destination address with its first bit(the LSB) low.  
A multicast address is defined as a destination address with its first bit(the LSB) high but the other 47  
bits are not all one. A broadcast address is defined as a destination address with its all 48 bits are one.  
All the three t ypes of t he packet r ecept i on ar e selectively determined by the configuration of  
the bit 3, 4 and 5 of the C18/CNCR register of the W89C840F.  
The C40/CPA0 and C44/CPA1 are used to store your own 48 bits Ethernet ID of the network  
node before starting to receive a packet. I t s cont ent s come from EEPROM after power-on reset.  
The mapping relationship among the 48 bits ID and the C40/CPA0 and C44/CPA1 are as  
following table.  
Bit 31~ 24  
32nd ~ 25th  
reserved  
Bit 23 ~ 16  
24th ~ 17th  
reserved  
Bit 15 ~ 8  
16th ~ 9th  
48th ~ 41st  
Bit 7 ~ 0  
8th ~ 1st  
C40/CPA0  
C44/CPA1  
40th ~ 33rd  
The incoming packet with unicast address will be accepted if the bit 3 of C18/CNCR is reset to  
low and the destination address of the incoming unicast packet has to match with the content of  
C40/CPA0 and C44/CPA1 setting.  
All of the incoming packet with unicast address will be accepted if the bit 3 of C18/CNCR is set  
to high.  
In broadcast case, to accept a packet with a broadcast destination address, the bit 5 of C18/CNCR  
must be set to high. Otherwise, the W89C840F will reject this broadcast packet.  
In multicast case, a packet with a multicast destination address will be accepted if the destination  
address is grouped into the selected group specified by the registers of C38/CMA0 and C3C/CMA1.  
These two registers are used to store the group mapping for the multicast packet.  
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